Table of Contents

• Design and evaluation of fault tolerance techniques for highly parallel architecturesJacob A. Abraham. [doi]
• Interlocked test generation and digital hardware synthesisFredrick J. Hill. 2-6 [doi]
• VLSI routing on the pipelined hypercube and related networksJoseph JáJá. 7-11 [doi]
• Dense layouts for series-parallel circuitsMichael A. Langston, Siddharthan Ramachandramurthi. 14-17 [doi]
• Area efficient binary tree layoutSourav Bhattacharya, Wei-Tek Tsai. 18-24 [doi]
• On wiring overlap layoutsCharles Chiang. 25-30 [doi]
• I/O bound binary tree layoutSourav Bhattacharya, Yoon-Hwa Choi, Wei-Tek Tsai. 31-36 [doi]
• A test controller board for TSSKevin T. Kornegay, Robert W. Brodersen. 38-42 [doi]
• General and efficient multiple list traversal for concurrent fault simulationPier Luca Montessoro, Silvano Gai. 43-48 [doi]
• An innovative user interface for fault simulation systemsPier Luca Montessoro. 49-53 [doi]
• A hierarchical multi-level test generation systemAntonio Lioy, Massimo Poncino. 54-59 [doi]
• On the complexity of a fault-tolerance model for multicomputer systemsA. Duksu Oh, Hyeong-Ah Choi, Abdol-Hossein Esfahanian. 62-67 [doi]
• Algorithm independent data flow mapping on a unified VLSI architectureSubramanian Mahalingham, Subra Ganesan. 68-73 [doi]
• A massively parallel and versatile architecture for computer visionA. Deb, Nam Ling. 74-79 [doi]
• Transforming disfigured and disoriented areas into routable switchboxesM. Starkey, Tony M. Carter. 82-87 [doi]
• On the generalized channel definition problemTeofilo F. Gonzalez, Mohammadreza Razzazi. 88-91 [doi]
• An efficient tabu search algorithm for graph bisectioningL. Tao, Y. C. Zhao, Krishnaiyan Thulasiraman, M. N. Shanmukha Swamy. 92-95 [doi]
• A new approach to timing driven partitioning of combinational logicNorbert Wehn, Manfred Glesner. 96-101 [doi]
• Optimal test set for stuck-at faults in VLSIK. S. Manjunath, Sterling R. Whitaker. 104-109 [doi]
• Transition count testing of CMOS combinational circuitsK. S. Manjunath, Damu Radharkrishnan. 110-114 [doi]
• An algebraic approach to test generation for sequential circuitsAntonio Lioy, Enrico Macii, Angelo Raffaele Meo, Matteo Sonza Reorda. 115-120 [doi]
• A low power CMOS correlatorJohn A. Canaris, Sterling R. Whitaker. 122-127 [doi]
• Implementation of fault-tolerant sequential circuits using programmable logic arraysN. Misra, Ashok K. Goel. 128-131 [doi]
• A CAD tool for designing large, fault-tolerant VLSI arraysPeter Poechmueller, G. K. Sharma, Manfred Glesner. 132-137 [doi]
• A VLSI implementation of a state variable filter algorithmHans-Jürgen Herpel, P. Windirsch, Manfred Glesner, J. Fuhrer, J. Busshardt. 138-143 [doi]
• A framework for 1-D compaction with forbidden region avoidance [VLSI layout]Susanne E. Hambrusch, Hung-Yi Tu. 146-151 [doi]
• A linear-time heuristic for rectilinear Steiner treesForbes D. Lewis, Wang Chia-Chi Pong, Nancy K. Van Cleave. 152-156 [doi]
• Routing non-convex grids without holesDee Parks, Miroslaw Truszczynski. 157-162 [doi]
• Four layer wiring using adjacent-layer viasTuang-Kuang Wu, Martin L. Brady. 163-168 [doi]
• A VLSI peripheral system for monitoring and stimulating action potentials of cultured neuronsM. A. AbuZaid, P. V. Vithalani, W. M. Gosney, L. L. Howard, Guenter W. Gross. 170-175 [doi]
• An architecture design using VLSI building blocks for dynamic programming neural networksChinchuan Chiu, Michael A. Shanblatt. 176-181 [doi]
• Applying Hopfield network to find the minimum cost coverage of a Boolean functionPong P. Chu. 182-185 [doi]
• Two-dimensional multirate systolic array design for artificial neural networksE. R. Khan, Nam Ling. 186-193 [doi]
• High frequency analog circuit design using QuickChipS. G. Burns. 196-201 [doi]
• A high resolution current stimulating probe for use in neural prosthesesC. Kim, D. Kang, Richard B. Brown, K. D. Wise. 202-206 [doi]
• Designing VLSI systolic arrays with complex processing elementsChang N. Zhang, Alen George Law, Ali Rezazadeh. 207-212 [doi]
• The 60° grid: routing channels in width d/√3K. D. Powers, Donna J. Brown, Martin L. Brady. 214-219 [doi]
• Topological via minimization and routingAhsan Abdullah, Sarma Sastry. 220-224 [doi]
• An experimental environment for design and analysis of global routing heuristicsJill David, Fillia Makedon, Bruno Codenotti, Mauro Leoncini. 225-230 [doi]
• Building block layout based on block compaction and two-adjacent-side channel routerShoichiro Yamada, Hirohisa Tanabe. 231-236 [doi]
• Testability profile estimation of VLSI circuits from fault coverageH. A. Farhat, H. Saidian. 238-242 [doi]
• Test plan generation and concurrent scheduling of tests in the presence of conflictsThomas Charles Wilson, Anupam Basu, Dilip K. Banerji, Jayanti C. Majithia. 243-248 [doi]
• A parallel algorithm for logic simulation on transputer networksS. Srinivas, Anupam Basu, Arogyaswami Paulraj, Lalit M. Patnaik. 249-254 [doi]
• Proving finite state machines correct with an automaton-based methodPaolo Camurati, Marco Gilli, Paolo Prinetto, Matteo Sonza Reorda. 255-258 [doi]
• Discrete Fourier transform processors using CORDICJeong-A. Lee, Kiseon Kim. 260-265 [doi]
• Uni-directional cube-connected cyclesSourav Bhattacharya, Yoon-Hwa Choi, Wei-Tek Tsai. 266-271 [doi]
• A poly to active region VLSI mask alignment test structureT. Ramesh. 278-283 [doi]
• An approach for multilevel logic cell optimization in module generatorsPeter Poechmueller, Manfred Glesner. 284-289 [doi]
• Gate matrix layout based on hierarchical net-list representationsShigeki Yamada, K. Yamazaki. 290-295 [doi]
• GALSY, an automatic layout generator of symbolic layouts from MOS circuit schematicsN. Baha, M. Beddiaf, A.-K. Gadiri. 296-300 [doi]
• Schematic driven layout for the custom VLSI design environmentJohn A. Canaris. 302-306 [doi]
• A reconstructive approach to automated design synthesisMichael R. Wick, B. D. Britt. 307-311 [doi]
• Genetic synthesis: performance-driven logic synthesis using genetic evolutionRam Vemuri, Ranga Vemuri. 312-317 [doi]
• Sequence invariant state machine compilerD. Buehler, Sterling R. Whitaker, John A. Canaris. 318-323 [doi]
• CMOS output buffer waveshapingLyle Albertson, Sterling R. Whitaker, R. Merrell. 326-327 [doi]
• Modeling of the transverse delays in modulation-doped heterojunction field-effect transistorsWei Xu, Ashok K. Goel. 328-329 [doi]
• Gate level representation of ECL circuits for fault modelingSankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya. 330-331 [doi]
• 'NCHIPSIM'-a microcomputer simulator of NMOS chip performance indicatorsAshok K. Goel, Fritz L. Schuermeyer. 332-333 [doi]
• Evaluation of silicon-on-sapphire enhancement JFETs for digital applicationsIhab E. Talkhan, Hoda S. Abdel-Aty-Zohdy. 334-335 [doi]
• Study of quaternary logic versus binary logicA. N. Gupte, Ashok K. Goel. 336-337 [doi]
• Design of fail-safe CMOS logic circuitsV. Bobin, Sterling R. Whitaker. 338-339 [doi]
• Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuitsAnupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia. 340-341 [doi]
• HADES-high-level architecture development and exploration systemPeter Poechmueller, Michael Held, Norbert Wehn, Manfred Glesner. 342-343 [doi]