Abstract is missing.
- Logic optimization by output phase assignment in dynamic logic synthesisRuchir Puri, Andrew Bjorksten, Thomas E. Rosser. 2-7 [doi]
- A new method towards achieving global optimality in technology mappingXiaoqing Wen, Kewal K. Saluja. 9-12 [doi]
- An efficient approach for moment-matching simulation of linear subnetworks with measured or tabulated dataGuowu Zheng, Qi-Jun Zhang, Michel S. Nakhla, Ramachandra Achar. 20-23 [doi]
- Automatic netlist extraction for measurement-based characterization of off-chip interconnectSteven D. Corey, Andrew T. Yang. 24-29 [doi]
- Analytical delay models for VLSI interconnects under ramp inputAndrew B. Kahng, Kei Masuko, Sudhakar Muddu. 30-36 [doi]
- Optimal non-uniform wire-sizing under the Elmore delay modelChung-Ping Chen, Hai Zhou, D. F. Wong. 38-43 [doi]
- Buffered Steiner tree construction with wire sizing for interconnect layout optimizationTakumi Okamoto, Jason Cong. 44-49 [doi]
- Clock tree synthesis for multi-chip modulesDaksh Lehther, Sachin S. Sapatnekar. 50-53 [doi]
- Sequential redundancy identification using recursive learningWanlin Cao, Dhiraj K. Pradhan. 56-62 [doi]
- Identification of unsettable flip-flops for partial scan and faster ATPGIsmed Hartanto, Vamsi Boppana, W. Kent Fuchs. 63-66 [doi]
- Simulation-based techniques for dynamic test sequence compactionElizabeth M. Rudnick, Janak H. Patel. 67-73 [doi]
- Tearing based automatic abstraction for CTL model checkingWoohyuk Lee, Abelardo Pardo, Jae-Young Jang, Gary D. Hachtel, Fabio Somenzi. 76-81 [doi]
- CTL model checking based on forward state traversalHiroaki Iwashita, Tsuneo Nakata, Fumiyasu Hirose. 82-87 [doi]
- VERILAT: verification using logic augmentation and transformationsDhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatterjee. 88-95 [doi]
- Software synthesis through task decomposition by dependency analysisYoungsoo Shin, Kiyoung Choi. 98-104 [doi]
- Synthesis of reusable DSP cores based on multiple behaviorsWei Zhao, Christos A. Papachristou. 103-108 [doi]
- Algorithms for address assignment in DSP code generationRainer Leupers, Peter Marwedel. 109-112 [doi]
- An approximate timing analysis method for datapath circuitsHakan Yalcin, John P. Hayes, Karem A. Sakallah. 114-118 [doi]
- Static timing analysis for self resetting circuitsVinod Narayanan, Barbara A. Chappell, Bruce M. Fleischer. 119-126 [doi]
- Timing verification of sequential domino circuitsDavid Van Campenhout, Trevor N. Mudge, Karem A. Sakallah. 127-132 [doi]
- Basic concepts for an HDL reverse engineering tool-setGunther Lehmann, Bernhard Wunder, Klaus D. Müller-Glaser. 134-141 [doi]
- Sensitivity analysis of iterative design processesEric W. Johnson, Jay B. Brockman. 142-145 [doi]
- Validation coverage analysis for complex digital designsRichard C. Ho, Mark Horowitz. 146-151 [doi]
- Clock-driven performance optimization in interactive behavioral synthesisHsiao-Ping Juan, Daniel Gajski, Viraphol Chaiyakul. 154-157 [doi]
- Register-transfer level estimation techniques for switching activity and power consumptionAnand Raghunathan, Sujit Dey, Niraj K. Jha. 158-165 [doi]
- Exploiting regularity for low-power designRenu Mehra, Jan M. Rabaey. 166-172 [doi]
- Optimization of custom MOS circuits by transistor sizingAndrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah. 174-180 [doi]
- An efficient approach to simultaneous transistor and interconnect sizingJason Cong, Lei He. 181-186 [doi]
- Generalized constraint generation in the presence of non-deterministic parasiticsEdoardo Charbon, Paolo Miliozzi, Enrico Malavasi, Alberto L. Sangiovanni-Vincentelli. 187-192 [doi]
- VLSI circuit partitioning by cluster-removal using iterative improvement techniquesShantanu Dutt, Wenyong Deng. 194-200 [doi]
- Multi-level spectral hypergraph partitioning with arbitrary vertex sizesJason Y. Zien, Martine D. F. Schlag, Pak K. Chan. 201-204 [doi]
- Minimum replication min-cut partitioningWai-Kei Mak, D. F. Wong. 205-210 [doi]
- Compact and complete test set generation for multiple stuck-faultsAlok Agrawal, Alexander Saldanha, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli. 212-219 [doi]
- GRASP - a new search algorithm for satisfiabilityJoão P. Marques Silva, Karem A. Sakallah. 220-227 [doi]
- Driving toward higher IDDQ test quality for sequential circuits: a generalized fault model and its ATPGHisashi Kondo, Kwang-Ting Cheng. 228-232 [doi]
- Comparing models of computationEdward A. Lee, Alberto L. Sangiovanni-Vincentelli. 234-241 [doi]
- Accurate interconnect modeling: towards multi-million transistor chips as microwave circuitsN. P. van der Meijs, T. Smedes. 244-251 [doi]
- A new method to express functional permissibilities for LUT based FPGAs and its applicationsShigeru Yamashita, Hiroshi Sawada, Akira Nagoya. 254-261 [doi]
- Fast Boolean optimization by rewiringShih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska. 262-269 [doi]
- Multi-level logic optimization for low power using local logic transformationsQi Wang, Sarma B. K. Vrudhula. 270-277 [doi]
- Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithmRoland W. Freund, Peter Feldmann. 280-287 [doi]
- A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuitsLuis Miguel Silveira, Mattan Kamon, Ibrahim M. Elfadel, Jacob White. 288-294 [doi]
- Computation of circuit waveform envelopes using an efficient, matrix-decomposed harmonic balance algorithmPeter Feldmann, Jaijeet S. Roychowdhury. 295-300 [doi]
- Post global routing crosstalk risk estimation and reductionTianxiong Xue, Ernest S. Kuh, Dongsheng Wang. 302-309 [doi]
- An optimal algorithm for river routing with crosstalk constraintsHai Zhou, D. F. Wong. 310-315 [doi]
- Jitter-tolerant clock routing in two-phase synchronous systemsJoe G. Xi, Wayne Wei-Ming Dai. 316-320 [doi]
- A design for testability technique for RTL circuits using control/data flow extractionIndradeep Ghosh, Anand Raghunathan, Niraj K. Jha. 329-336 [doi]
- Bit-flipping BISTHans-Joachim Wunderlich, Gundolf Kiefer. 337-343 [doi]
- Using complete-1-distinguishability for FSM equivalence checkingPranav Ashar, Aarti Gupta, Sharad Malik. 346-353 [doi]
- Improved reachability analysis of large finite state machinesGianpiero Cabodi, Paolo Camurati, Stefano Quer. 354-360 [doi]
- ACV: an arithmetic circuit verifierYirng-An Chen, Randal E. Bryant. 361-365 [doi]
- Hierarchical statistical characterization of mixed-signal circuits using behavioral modelingEric Felt, Stefano Zanella, Carlo Guardiani, Alberto L. Sangiovanni-Vincentelli. 374-380 [doi]
- A novel dimension reduction technique for the capacitance extraction of 3D VLSI interconnectsWei Hong II, Weikai Sun, Zhenhai Zhu, Hao Ji, Ben Song, Wayne Wei-Ming Dai. 381-386 [doi]
- Inaccuracies in power estimation during logic synthesisDaniel Brand, Chandramouli Visweswariah. 388-394 [doi]
- Clock skew optimization for ground bounce controlAshok Vittal, Hein Ha, Forrest Brewer, Malgorzata Marek-Sadowska. 395-399 [doi]
- Heterogeneous built-in resiliency of application specific programmable processorsKyosun Kim, Ramesh Karri, Miodrag Potkonjak. 406-411 [doi]
- Unit delay simulation with the inversion algorithmWilliam J. Schilp, Peter M. Maurer. 412-417 [doi]
- An observability-based code coverage metric for functional simulationSrinivas Devadas, Abhijit Ghosh, Kurt Keutzer. 418-425 [doi]
- Latch optimization in circuits generated from high-level descriptionsEllen Sentovich, Horia Toma, Gérard Berry. 428-435 [doi]
- Synthesis using sequential functional modules (SFMs)Samit Chaudhuri, Michael Quayle. 436-441 [doi]
- An algorithm for synthesis of system-level interface circuitsKi-Seok Chung, Rajesh K. Gupta, C. L. Liu. 442-447 [doi]
- An algorithm for power estimation in switched-capacitor circuitsChad Young, Giorgio Casinovi, Jonathan Fowler, Paul Kerstetter. 450-454 [doi]
- Semi-analytical techniques for substrate characterization in the design of mixed-signal ICsEdoardo Charbon, Ranjit Gharpurey, Alberto L. Sangiovanni-Vincentelli, Robert G. Meyer. 455-462 [doi]
- A video driver system designed using a top-down, constraint-driven methodologyIasson Vassiliou, Henry Chang, Alper Demir, Edoardo Charbon, Paolo Miliozzi, Alberto L. Sangiovanni-Vincentelli. 463-468 [doi]
- Hierarchical partitioningDirk Behrens, Klaus Harbich, Erich Barke. 470-477 [doi]
- Hybrid floorplanning based on partial clustering and module restructuringTakayuki Yamanouchi, Kazuo Tamakashi, Takashi Kambe. 478-483 [doi]
- Module placement on BSG-structure and IC layout applicationsShigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani. 484-491 [doi]
- Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faultsMukund Sivaraman, Andrzej J. Strojwas. 494-501 [doi]
- SIGMA: a simulator for segment delay faultsKeerthi Heragu, Janak H. Patel, Vishwani D. Agrawal. 502-508 [doi]
- Zamlog: a parallel algorithm for fault simulation based on ZambeziMinesh B. Amin, Bapiraju Vinnakota. 509-512 [doi]
- Metrics, techniques and recent developments in mixed-signal testingGordon W. Roberts. 514-521 [doi]
- Noise in deep submicron digital designKenneth L. Shepard, Vinod Narayanan. 524-531 [doi]
- Intranets and EDA: impact, application, and technologyDavid C. Ku, James A. Rowson. 534 [doi]
- Digital sensitivity: predicting signal interaction using functional analysisDesmond Kirkpatrick, Alberto L. Sangiovanni-Vincentelli. 536-541 [doi]
- Efficient solution of systems of Boolean equationsScott Woods, Giorgio Casinovi. 542-546 [doi]
- Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functionsAmit Narayan, Jawahar Jain, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli. 547-554 [doi]
- Simulation and sensitivity analysis of transmission line circuits by the characteristics methodJun-Fa Mao, Janet Meiling Wang, Ernest S. Kuh. 556-562 [doi]
- A general dispersive multiconductor transmission line model for interconnect simulation in SPICEMustafa Celik, Andreas C. Cangellaris. 563-568 [doi]
- Efficient time-domain simulation of frequency-dependent elementsSharad Kapur, David E. Long, Jaijeet S. Roychowdhury. 569-573 [doi]
- Stratified random sampling for power estimationChih-Shun Ding, Cheng-Ta Hsieh, Qing Wu, Massoud Pedram. 576-582 [doi]
- Statistical sampling and regression analysis for RT-level power evaluationCheng-Ta Hsieh, Qing Wu, Chih-Shun Ding, Massoud Pedram. 583-588 [doi]
- Expected current distributions for CMOS circuitsDennis J. Ciplickas, Ronald A. Rohrer. 589-592 [doi]
- Metrology for analog module testing using analog testability busChauchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tzu Ting. 594-599 [doi]
- ABILBO: Analog BuILt-in Block ObserverMarcelo Lubaszewski, Salvador Mir, Leandro Pulz. 600-603 [doi]
- Design of robust test criteria in analog testingWalter M. Lindermeir. 604-611 [doi]
- Metamorphosis: state assignment by retiming and re-encodingBalakrishnan Iyer, Maciej J. Ciesielski. 614-617 [doi]
- The case for retiming with explicit reset circuitryVigyan Singhal, Sharad Malik, Robert K. Brayton. 618-625 [doi]
- Polarized observability don t caresHarm Arts, Michel R. C. M. Berkelaar, C. A. J. van Eijk. 626-631 [doi]
- Power optimization in disk-based real-time application specific systemsInki Hong, Miodrag Potkonjak. 634-637 [doi]
- A hierarchical functional structuring and partitioning approach for multiple-FPGA implementationsWen-Jong Fang, Allen C.-H. Wu. 638-643 [doi]
- Generation of BDDs from hardware algorithm descriptionsShin-ichi Minato. 644-649 [doi]
- Directional bias and non-uniformity in FPGA global routing architecturesVaughn Betz, Jonathan Rose. 652-659 [doi]
- Width minimization of two-dimensional CMOS cells using integer programmingAvaneendra Gupta, John P. Hayes. 660-667 [doi]
- Interchangeable pin routing with application to package layoutMan-Fai Yu, Joel Darnauer, Wayne Wei-Ming Dai. 668-673 [doi]
- A coloring approach to the structural diagnosis of interconnectsXiao-Tao Chen, Fabrizio Lombardi. 676-680 [doi]
- Integrated fault diagnosis targeting reduced simulationVamsi Boppana, W. Kent Fuchs. 681-684 [doi]
- An efficient, bus-layout based method for early diagnosis of bussed driver shorts in printed circuit boardsKanad Chakraborty, Pinaki Mazumder. 685-688 [doi]
- Design for manufacturability in submicron domainWojciech Maly, Hans T. Heineken, Jitendra Khare, Pranab K. Nag. 690-697 [doi]
- Embedded tutorial: Speed - new paradigms in design for performanceRalph H. J. M. Otten, Lukas P. P. P. van Ginneken, Narendra V. Shenoy. 700 [doi]