Abstract is missing.
- Two ASIC for Low and Middle Levels of Real Time Image ProcessingP. Lamaty, B. Mazar, Didier Demigny, Lounis Kessal, M. Karabernou. 3-14
- 64×64 Pixels General Purpose Digital Vision ChipTakashi Komuro, Masatoshi Ishikawa. 15-26
- A Vision System on Chip for Industrial ControlEric Senn, Eric Martin. 27-38
- Fast Recursive Implementation of the Gaussian FilterDidier Demigny, Lounis Kessal, J. Pons. 39-49
- A Dynamically Reconfigurable Architecture for Low-Power Multimedia TerminalsRaphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys. 51-62
- Dynamically Reconfigurable Architectures for Digital Signal Processing ApplicationsGilles Sassatelli, Lionel Torres, Pascal Benoit, Gaston Cambon, Michel Robert, Jérôme Galy. 63-74
- Reconfigurable Architecture Using High Speed FPGALounis Kessal, R. Bourguiba, Didier Demigny, N. Boudouani, M. Karabernou. 75-86
- Design Technology for Systems-on-ChipRaul Camposano, Don MacMillen. 87-96
- Distributed Collaborative Design over Cave2 FrameworkLeandro Soares Indrusiak, Jürgen Becker, Manfred Glesner, Ricardo Augusto da Luz Reis. 97-108
- High Performance Java Hardware Engine and Software Kernel for Embedded SystemsMorgan Hirosuke Miki, Motoki Kimura, Takao Onoye, Isao Shirakawa. 109-120
- An Object-Oriented Methodology for Modeling the Precise Behavior of Processor ArchitecturesJoão Cláudio Soares Otero, Flávio Rech Wagner. 121-132
- Interconnect Capacitance Modelling in a VDSM CMOS TechnologyDavid Bernard, Christian Landrault, Pascal Nouet. 133-144
- Abstract Communication Model and Automatic Interface generation for IP integration in Hardware/Software Co-designCristiano C. de Araujo, Edna Barros. 145-156
- An Evolutionary Approach for Pareto-optimal Configurations in SOC PlatformsGiuseppe Ascia, Vincenzo Catania, Maurizio Palesi. 157-168
- Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 µm Bulk and Silicon-On-Insulator CMOS TechnologiesAmaury Nève, Denis Flandre. 169-180
- A Standardized Co-simulation BackboneBraulio Adriano de Mello, Flávio Rech Wagner. 181-192
- Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared MemorySamy Meftali, Ferid Gharsalli, Frédéric Rousseau, Ahmed Amine Jerraya. 193-204
- Modeling Power Dynamics for an Embedded DSP Processor Core. An Empirical ModelCatherine H. Gebotys, Radu Muresan. 205-216
- Power Consumption Model for the DSP OAK ProcessorPatricia Guitton-Ouhamou, Cécile Belleudy, Michel Auguin. 217-228
- Integration of Robustness in the Design of a CellJ. M. Dutertre, F. M. Roche, Guy Cathebras. 229-239
- Impact of Technology Spreading on MEMS design RobustnessVincent Beroulle, Laurent Latorre, M. Dardalhon, C. Oudea, G. Perez, F. Pressecq, Pascal Nouet. 241-251
- A New Efficient VLSI Architecture for Full Search Block Matching Motion EstimationNuno Roma, Leonel Sousa. 253-264
- Design Considerations of a Low-Complexity, Low-Power Integer Turbo DecoderStephen M. Pisuk, Peter H. Wu. 265-276
- Low-Voltage Embedded-RAM Technology: Present and FutureKiyoo Itoh, Hiroyuki Mizuno. 277-288
- Low-Voltage 0, 25 µm CMOS Improved Power Adaptive Issue Queue for Embedded MicroprocessorsBrian W. Curran, Mary Gifaldi, Jason Martin, Alper Buyuktosunoglu, Martin Margala, David H. Albonesi. 289-300
- Gate Sizing for Low Power DesignPhilippe Maurine, Nadine Azémard, Daniel Auvergne. 301-312
- Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication SystemsJean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin. 313-324
- Feasible Delay Bound DefinitionNadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne. 325-335
- CMOS Mixed-signal Circuits Design on a Digital Array Using Minimum TransistorsJung Hyun Choi, Sergio Bampi. 337-347
- A VHDL-AMS Case Study: The Incremental Design of an Efficient 3:::rd::: Generation MOS Model of a Deep Sub Micron TransistorChristophe Lallement, François Pêcheux, Yannick Hervé. 349-360
- Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal WidthsPeer Johannsen, Rolf Drechsler. 361-374
- Functional Test Generation using Constraint Logic ProgrammingZhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre. 375-387
- An Industrial Approach to Core-Based System Chip TestingErik Jan Marinissen. 389-400
- Power-Constrained Test Scheduling for SoCs Under a no session SchemeMarie-Lise Flottes, Julien Pouget, Bruno Rouzeyre. 401-412
- Random Adjacent Sequences: An Efficient Solution for Logic BISTRené David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. 413-424
- On-chip Generator of a Saw-Tooth Test Stimulus for ADC BISTFlorence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell. 425-436
- Built-in Test of Analog Non-Linear Circuits in a SOC EnvironmentLuigi Carro, André C. Nácul, Daniel Janner, Marcelo Lubaszewski. 437-448
- Design of a Fast CMOS APS Imager for High Speed Laser DetectionsB. Casadei, J. P. Le Normand, Y. Hu, B. Cunin. 449-460
- Noise optimisation of a piezoresistive CMOS MEMS for magnetic field sensingVincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet. 461-472