Abstract is missing.
- ISQED 2010 fellow award recipientDaniela De Venuto. [doi]
- ISQED quality award recipient (IQ-Award 2010)Leon O. Chua. [doi]
- Welcome to ISQED 2010Kamesh V. Gadepally, Lalitha Immaneni, Pallab Chatterjee, George Alexiou, Ali Iranmanesh. [doi]
- Limits of bias based assist methods in nano-scale 6T SRAMRandy W. Mann, Satyanand Nalam, Jiajing Wang, Benton H. Calhoun. 1-8 [doi]
- Variability resilient low-power 7T-SRAM design for nano-scaled technologiesTouqeer Azam, Binjie Cheng, David R. S. Cumming. 9-14 [doi]
- Robust importance sampling for efficient SRAM yield analysisTakanori Date, Shiho Hagiwara, Kazuya Masu, Takashi Sato. 15-21 [doi]
- An accurate modeling method utilizing application-specific statistical information and its application to SRAM yield estimationHidetoshi Matsuoka, Hiroshi Ikeda, Hiroyuki Higuchi, Yoshinori Tomita. 22-28 [doi]
- Adaptive power gating for function units in a microprocessorKimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura. 29-37 [doi]
- A dual-level adaptive supply voltage system for variation resilienceKyu-Nam Shim, Jiang Hu, José Silva-Martínez. 38-43 [doi]
- A low power charge-redistribution ADC with reduced capacitor arrayMallik Kandala, Ramgopal Sekar, Chenglong Zhang, Haibo Wang. 44-48 [doi]
- Leakage current analysis for intra-chip wireless interconnectsAnkit More, Baris Taskin. 49-53 [doi]
- Toward effective utilization of timing exceptions in design optimizationKwangok Jeong, Andrew B. Kahng, Seokhyeong Kang. 54-61 [doi]
- Useful clock skew optimization under a multi-corner multi-mode design frameworkWeixiang Shen, Yici Cai, Wei Chen, Yongqiang Lu, Qiang Zhou, Jiang Hu. 62-68 [doi]
- Clock buffer polarity assignment considering the effect of delay variationsMinseok Kang, Taewhan Kim. 69-74 [doi]
- Linear time calculation of state-dependent power distribution network capacitanceShiho Hagiwara, Koh Yamanaga, Ryo Takahashi, Kazuya Masu, Takashi Sato. 75-80 [doi]
- Implementing self-testing and self-repairable analog circuits on field programmable analog array platformsVenkata Naresh Mudhireddy, Saravanan Ramamoorthy, Haibo Wang. 81-86 [doi]
- BSIM4-based lateral diode model for LNA co-designed with ESD protection circuitMing-Ta Yang, Yang Du, Charles Teng, Tony Chang, Eugene Worley, Ken Liao, You-Wen Yau, Geoffrey Yeap. 87-91 [doi]
- Hot carrier effects on CMOS phase-locked loop frequency synthesizersYang Liu, Ashok Srivastava. 92-98 [doi]
- A novel all-digital fractional-N frequency synthesizer architecture with fast acquisition and low spurJun Zhao, Yong-Bin Kim. 99-102 [doi]
- Photomasks and the enablement of circuit design complexityPeter Buck, Franklin Kalk, Craig West. 103-107 [doi]
- High performance source optimization using a gradient-based method in optical lithographyYao Peng, Jinyu Zhang, Yan Wang, Zhiping Yu. 108-113 [doi]
- Yield-constrained digital circuit sizing via sequential geometric programmingYu Ben, Laurent El Ghaoui, Kameshwar Poolla, Costas J. Spanos. 114-121 [doi]
- Assessing chip-level impact of double patterning lithographyKwangok Jeong, Andrew B. Kahng, Rasit Onur Topaloglu. 122-130 [doi]
- A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overheadJawar Singh, Dilip S. Aswar, Saraju P. Mohanty, Dhiraj K. Pradhan. 131-138 [doi]
- Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operationSatyanand Nalam, Vikas Chandra, Cezary Pietrzyk, Robert C. Aitken, Benton H. Calhoun. 139-146 [doi]
- A robust and low power dual data rate (DDR) flip-flop using c-elementsSrikanth V. Devarapalli, Payman Zarkesh-Ha, Steven C. Suddarth. 147-150 [doi]
- Optimizing power and throughput for m-out-of-n encoded asynchronous circuitsJun Xu, Ge Zhang, Weiwu Hu. 151-157 [doi]
- Simultaneous extraction of effective gate length and low-field mobility in non-uniform devicesVivek Joshi, Kanak Agarwal, Dennis Sylvester. 158-162 [doi]
- Statistical static timing analysis flow for transistor level macros in a microprocessorVivek S. Nandakumar, David Newmark, Yaping Zhan, Malgorzata Marek-Sadowska. 163-170 [doi]
- A framework for logic-aware layout analysisPatrick Gibson, Ziyang Lu, Fedor Pikus, Sridhar Srinivasan. 171-175 [doi]
- P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILPGarima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan. 176-183 [doi]
- A yield improvement methodology based on logic redundant repair with a repairable scan flip-flop designed by push ruleMasanori Kurimoto, Jun Matsushima, Shigeki Ohbayashi, Yoshiaki Fukui. 184-190 [doi]
- A fault-tolerant structure for reliable multi-core systems based on hardware-software co-designBingbing Xia, Fei Qiao, Huazhong Yang, Hui Wang. 191-197 [doi]
- Condition-based dummy fill insertion method based on ECP and CMP predictive modelsIzumi Nitta, Yuji Kanazawa, Daisuke Fukuda, Toshiyuki Shibuya, Naoki Idani, Masaru Ito, Osamu Yamasaki, Norihiro Harada, Takanori Hiramoto. 198-205 [doi]
- Analysis and modeling of a Low Voltage Triggered SCR ESD protection clamp with the very fast Transmission Line Pulse measurementJae Young Park, Jong-Kyu Song, Chang-Soo Jang, Young-Sang Son, Dae-Woo Kim. 206-210 [doi]
- On the design of different concurrent EDC schemes for S-Box and GF(p)Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir, Saraju P. Mohanty, Dhiraj K. Pradhan. 211-218 [doi]
- Adaptive HCI-aware power gating structureKyung Ki Kim, Haiqing Nan, Ken Choi. 219-224 [doi]
- Soft error rate determination for nanoscale sequential logicFan Wang, Vishwani D. Agrawal. 225-230 [doi]
- Ultra low-voltage, rail-to-rail input/output stage Operational Transconductance Amplifier (OTA) with high linearity and its application in a Gm-C filterFarzan Rezaei, Seyed Javad Azhari. 231-236 [doi]
- A novel two-dimensional scan-control scheme for test-cost reductionChia-Yi Lin, Hung-Ming Chen. 237-243 [doi]
- Accelerating trace computation in post-silicon debugJohnny J. W. Kuan, Steven J. E. Wilton, Tor M. Aamodt. 244-249 [doi]
- Structural fault collapsing by superposition of BDDs for test generation in digital circuitsRaimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman. 250-257 [doi]
- A novel probabilistic SET propagation methodSreenivas Gangadhar, Spyros Tragoudas. 258-263 [doi]
- Formal verification of Full-Wave Rectifier using SPICE circuit simulation tracesKusum Lata, H. S. Jamadagni. 264-270 [doi]
- OBT implementation on an OTA-C band-pass filterPablo A. Petrashin, Gabriela Peretti, Eduardo Romero. 271-276 [doi]
- Fast block-iterative domain decomposition algorithm for IR drop analysis in large power gridYu Zhong, Martin D. F. Wong. 277-283 [doi]
- A non-parametric approach to behavioral device modelingDragoljub Gagi Drmanac, Brendon Bolin, Li-C. Wang. 284-290 [doi]
- Robust gate sizing by Uncertainty Second Order ConeJin Sun, Janet Meiling Wang. 291-298 [doi]
- Is built-in logic redundancy ready for prime time?Chris Allsup. 299-306 [doi]
- Variation-aware speed binning of multi-core processorsJohn Sartori, Aashish Pant, Rakesh Kumar, Puneet Gupta. 307-314 [doi]
- Use of scalable Parametric Measurement Macro to improve semiconductor technology characterization and product testJeanne Bickford, Nazmul Habib, John Goss, Robert McMahon, Rajiv V. Joshi, Rouwaida Kanj. 315-319 [doi]
- Accurate multi-specification DPPM estimation using layered sampling based simulationEnder Yilmaz. 320-326 [doi]
- Scalability of PCMO-based resistive switch device in DSM technologiesYiran Chen, Wei Tian, Hai Li, XiaoBin Wang, Wenzhong Zhu. 327-332 [doi]
- A low power system with adaptive data compression for wireless monitoring of physiological signals and its application to wireless electroencephalographyJeremy R. Tolbert, Pratik Kabali, Simeranjit Brar, Saibal Mukhopadhyay. 333-341 [doi]
- Modeling and analysis of III-V logic FETs for devices and circuits: Sub-22nm technology III-V SRAM cell designSaeroonter Oh, Jeongha Park, S. Simon Wong, H.-S. Philip Wong. 342-346 [doi]
- Die-level leakage power analysis of FinFET circuits considering process variationsPrateek Mishra, Ajay N. Bhoj, Niraj K. Jha. 347-355 [doi]
- Using time-aware memory sensing to address resistance drift issue in multi-level phase change memoryWei Xu, Tong Zhang. 356-361 [doi]
- Minimizing the power consumption of a Chip Multiprocessor under an average throughput constraintMohammad Ghasemazar, Ehsan Pakbaznia, Massoud Pedram. 362-371 [doi]
- Design of low-power variation tolerant signal processing systems with adaptive finite word-length configurationYang Liu, Jibang Liu, Tong Zhang. 372-379 [doi]
- Quality-driven methodology for demanding accelerator designLech Józwiak, Yahya Jan. 380-389 [doi]
- Thermal-aware job allocation and scheduling for three dimensional chip multiprocessorShaobo Liu, Jingyi Zhang, Qing Wu, Qinru Qiu. 390-398 [doi]
- Thermal-aware lifetime reliability in multicore systemsShengquan Wang, Jian-Jia Chen. 399-405 [doi]
- A comprehensive model for gate delay under process variation and different driving and loading conditionsMingzhi Gao, Zuochang Ye, Yao Peng, Yan Wang, Zhiping Yu. 406-412 [doi]
- Skew analysis and bounded skew constraint methodology for rotary clocking technologyVinayak Honkote, Baris Taskin. 413-417 [doi]
- A MATLAB-based technique for defect level estimation using data mining of test fallout data versus fault coverageKanad Chakraborty. 418-421 [doi]
- Constraint analysis and debugging for multi-million instance SoC designsLong Fei, Loa Mize, Cho Moon, Bill Mullen, Sonia Singhal. 422-427 [doi]
- Variation aware guard -banding for SOC static timing analysisVee Kin Wong, Siong Kiong Teng. 428-431 [doi]
- Asymmetric issues of FinFET device after hot carrier injection and impact on digital and analog circuitsChenyue Ma, Hao Wang, Xiufang Zhang, Frank He, Yadong He, Xing Zhang, Xinnan Lin. 432-436 [doi]
- A novel low voltage current compensated high performance current mirror/NICKhalil Monfaredi, Hassan Faraji Baghtash, Seyed Javad Azhari. 437-442 [doi]
- Domino gate with modified voltage keeperJinhui Wang, Wuchen Wu, Na Gong, Ligang Hou. 443-446 [doi]
- Leakage temperature dependency modeling in system level analysisHuang Huang, Gang Quan, Jeffrey Fan. 447-452 [doi]
- Process variation tolerant on-chip communication using receiver and driver reconfigurationEthiopia Nigussie, Juha Plosila, Jouni Isoaho. 453-460 [doi]
- Calibration of on-chip thermal sensors using process monitoring circuitsBasab Datta, Wayne P. Burleson. 461-467 [doi]
- New SRAM design using body bias technique for ultra low power applicationsFarshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Yngvar Berg, Tuan Vu Cao. 468-471 [doi]
- Body bias driven design synthesis for optimum performance per areaMaurice Meijer, José Pineda de Gyvez. 472-477 [doi]
- Methodology to ensure circuit robustness and exceptional silicon quality while proliferating designs across process revisions with high productivityNitin Srimal. 478-482 [doi]
- A multilevel multilayer partitioning algorithm for three dimensional integrated circuitsYu Cheng Hu, Yin Lin Chung, Mely Chen Chi. 483-487 [doi]
- Low power clock gates optimization for clock tree distributionSiong Kiong Teng, Norhayati Soin. 488-492 [doi]
- An innovative method to automate the waiver of IP-level DRC violationsJohn Ferguson, Sandeep Koranne, David Abercrombie. 493-498 [doi]
- Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networksHouman Homayoun, Shahin Golshan, Eli Bozorgzadeh, Alexander V. Veidenbaum, Fadi J. Kurdahi. 499-507 [doi]
- Antenna Violation Avoidance/Fixing for X-clock routingChia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee. 508-514 [doi]
- Synthesis and formal verification of on-chip protocol transducers through decomposed specificationMasahiro Fujita, Hideo Tanida, Fei Gao, Tasuku Nishihara, Takeshi Matsumoto. 515-523 [doi]
- Level matrix propagation for reliability analysis of nano-scale circuits based on probabilistic transfer matrixHicham Ezzat, Lirida A. B. Naviner. 524-527 [doi]
- The design of a low-power low-noise phase lock loopAbishek Mann, Amit Karalkar, Lili He 0001, Morris Jones. 528-531 [doi]
- Novel low-power 12-bit SAR ADC for RFID tagsDaniela De Venuto, Eduard Stikvoort, David Tio Castro, Youri Ponomarev. 532-537 [doi]
- Adaptive task allocation for multiprocessor SoCsTongquan Wei, Yonghe Guo, Xiaodao Chen, Shiyan Hu. 538-543 [doi]
- Real-time dynamic hybrid BiST solution for Very-Low-Cost ATE production testing of A/D converters with controlled DPPMSachin Dileep Dasnurkar, Jacob A. Abraham. 562-569 [doi]
- On evaluating speed path detection of structural testsJing Zeng, Jing Wang, Chia-Ying Chen, Michael Mateja, Li-C. Wang. 570-576 [doi]
- Slack-based approach for peak power reduction during transition fault testingManu Baby, Vijay Sarathi. 577-581 [doi]
- Case studies of mixed-signal DFTRamyanshu Datta, Mahit Warhadpande, Dale Heaton, S. Aarthi, Ram Jonnavithula. 582-589 [doi]
- Efficient hierarchical discretization of off-chip power delivery network geometries for 2.5D electrical analysisMosin Mondal, James Pingenot, Vikram Jandhyala. 590-597 [doi]
- Yield improvement of 3D ICs in the presence of defects in through signal viasRajeev K. Nain, Shantesh Pinge, Malgorzata Chrzanowska-Jeske. 598-605 [doi]
- A negotiated congestion based router for simultaneous escape routingQiang Ma, Tan Yan, Martin D. F. Wong. 606-610 [doi]
- Dynamic voltage (IR) drop analysis and design closure: Issues and challengesS. K. Nithin, Gowrysankar Shanmugam, Sreeram Chandrasekar. 611-617 [doi]
- Analog placement and global routing considering wiring symmetryYu-Ming Yang, Iris Hui-Ru Jiang. 618-623 [doi]
- Worst-case noise prediction with non-zero current transition times for early power distribution system verificationPeng Du, Xiang Hu, Shih-Hung Weng, Amirali Shayan Arani, Xiaoming Chen, A. Ege Engin, Chung-Kuan Cheng. 624-631 [doi]
- Fixed outline multi-bend bus driven floorplanningWenxu Sheng, Sheqin Dong, Yuliang Wu, Satoshi Goto. 632-637 [doi]
- Scalable methods for the analysis and optimization of gate oxide breakdownJianxin Fang, Sachin S. Sapatnekar. 638-645 [doi]
- Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability considerationHiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye. 646-651 [doi]
- Multi-corner, energy-delay optimized, NBTI-aware flip-flop designHamed Abrishami, Safar Hatami, Massoud Pedram. 652-659 [doi]
- Signal probability control for relieving NBTI in SRAM cellsYuji Kunitake, Toshinori Sato, Hiroto Yasuura. 660-666 [doi]
- Early-stage determination of current-density criticality in interconnectsGöran Jerke, Jens Lienig. 667-674 [doi]
- Automated silicon debug data analysis techniques for a hardware data acquisition environmentYu-Shen Yang, Brian Keng, Nicola Nicolici, Andreas G. Veneris, Sean Safarpour. 675-682 [doi]
- Layout-aware Illinois Scan design for high fault coverage coverageSavita Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty. 683-688 [doi]
- Multi-degree smoother for low power consumption in single and multiple scan-chains BISTAbdallatif S. Abu-Issa, Steven F. Quigley. 689-696 [doi]
- Multiplexed trace signal selection using non-trivial implication-based correlationSandesh Prabhakar, Michael S. Hsiao. 697-704 [doi]
- Modeling and verification of industrial flash memoriesSandip Ray, Jayanta Bhadra, Thomas Portlock, Ronald Syzdek. 705-712 [doi]
- Auto-BET-AMS: An automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design frameworkAngada B. Sachid, Rajesh Amratlal Thakker, Chaitanya Sathe, Maryam Shojaei Baghini, Dinesh Kumar Sharma, V. Ramgopal Rao, Mahesh B. Patil. 713-720 [doi]
- UC-PHOTON: A novel hybrid photonic network-on-chip for multiple use-case applicationsShirish Bahirat, Sudeep Pasricha. 721-729 [doi]
- Hellfire: A design framework for critical embedded systems applicationsAlexandra Aguiar, Sergio Johann Filho, Felipe G. Magalhaes, Thiago D. Casagrande, Fabiano Hessel. 730-737 [doi]
- Slack allocation for yield improvement in NoC-based MPSoCsBrett H. Meyer, Adam S. Hartman, Donald E. Thomas. 738-746 [doi]
- Power-yield optimization in MPSoC task scheduling under process variationMahmoud Momtazpour, Esmaeel Sanaei, Maziar Goudarzi. 747-754 [doi]
- A revisit to the primal-dual based clock skew scheduling algorithmMin Ni, Seda Ogrenci Memik. 755-764 [doi]
- Clock buffer polarity assignment considering capacitive loadJianchao Lu, Baris Taskin. 765-770 [doi]
- A low power clock network placement frameworkDawei Liu, Qiang Zhou, Yongqiang Lu, Jinian Bian. 771-776 [doi]
- Clock routing for structured ASICs with via-configurable fabricsRung-Bin Lin, I-Wei Lee, Wen-Hao Chen. 777-784 [doi]
- Analysis of power supply induced jitter in actively de-skewed multi-core systemsDerek Chan, Matthew R. Guthaus. 785-790 [doi]
- Analyzing and minimizing effects of temperature variation and NBTI on active leakage power of power-gated circuitsAbhishek A. Sinkar, Nam Sung Kim. 791-796 [doi]
- Signal processing methods and hardware-structure for on-line characterization of thermal gradients in many-core processorsMinki Cho, Saibal Mukhopadhyay. 797-803 [doi]
- A convex optimization framework for leakage aware thermal provisioning in 3D multicore architecturesSanghamitra Roy, Koushik Chakraborty. 804-811 [doi]
- Improving the process variation tolerability of flip-flops for UDSM circuit designEun Ju Hwang, Wook Kim, Young-Hwan Kim. 812-817 [doi]
- Interconnect delay and slew metrics using the extreme value distributionJun-Kuei Zeng, Chung-Ping Chen. 818-823 [doi]
- Design methodology of variable latency adders with multistage function speculationYongpan Liu, YiNan Sun, Yihao Zhu, Huazhong Yang. 824-830 [doi]
- Accurate statistical soft error rate (SSER) analysis using a quasi-Monte Carlo framework with quality cell modelsYu-Hsin Kuo, Huan-Kai Peng, Charles H.-P. Wen. 831-838 [doi]
- Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolutionRyo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye. 839-844 [doi]
- Design of a fault-tolerant coarse-grainedSyed M. A. H. Jafri, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement. 845-852 [doi]
- Comparative analysis and study of metastability on high-performance flip-flopsDavid Li, Pierce Chuang, Manoj Sachdev. 853-860 [doi]
- Reliability analysis of analog circuits by lifetime yield prediction using worst-case distance degradation rateXin Pan, Helmut Graeb. 861-865 [doi]
- The compatibility analysis of thread migration and DVFS in multi-core processorDongkeun Oh, Charlie Chung-Ping Chen, NamSung Kim, Yu Hen Hu. 866-871 [doi]
- Analog behavioral modeling flow using statistical learning methodHui Li, Makram Mansour, Sury Maturi, Li-C. Wang. 872-878 [doi]
- Coprocessor design space exploration using high level synthesisAvinash Lakshminarayana, Sumit Ahuja, Sandeep K. Shukla. 879-884 [doi]
- Methodology from chaos in IC implementationKwangok Jeong, Andrew B. Kahng. 885-892 [doi]