Abstract is missing.
- A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMsArijit Banerjee, Mahmut E. Sinangil, John W. Poulton, C. Thomas Gray, Benton H. Calhoun. 1-8 [doi]
- A new era of computing: Are you "ready now" to build a smarter and secured enterprise?Jacqueline Woods, Sridhar Iyengar, Amit Sinha, Subhasish Mitra, Stacy Cannady. 1 [doi]
- Exploiting static and dynamic locality of timing errors in robust L1 cache designHu Chen, Sanghamitra Roy, Koushik Chakraborty. 9-15 [doi]
- A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvementYohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto. 16-23 [doi]
- 40nm Ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCUYoshisato Yokoyama, Yuichiro Ishii, Hidemitsu Kojima, Atsushi Miyanishi, Yoshiki Tsujihashi, Shinobu Asayama, Kazutoshi Shiba, Koji Tanaka, Tatsuya Fukuda, Koji Nii, Kazumasa Yanagisawa. 24-31 [doi]
- Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM cachesPeyman Pouyan, Esteve Amat, Enrique Barajas, Antonio Rubio. 32-38 [doi]
- Modeling, design and verification platform using SystemC AMSYao Li, Ramy Iskander, Marie-Minerve Louërat. 39-46 [doi]
- On application of one-class SVM to reverse engineering-based hardware Trojan detectionChongxi Bao, Domenic Forte, Ankur Srivastava. 47-54 [doi]
- Employing a Timed Colored Petri Net to accomplish an accurate model for Network-on-Chip performance evaluationJarbas Silveira, Paulo César Cortez, Giovanni Cordeiro Barroso, César A. M. Marcon. 55-59 [doi]
- Integrated particle swarm optimization (i-PSO): An adaptive design space exploration framework for power-performance tradeoff in architectural synthesisAnirban Sengupta, Vipul Kumar Mishra. 60-67 [doi]
- Modeling and analysis of system stability in a distributed power delivery network with embedded digital linear regulatorsSaad Bin Nasir, Youngtak Lee, Arijit Raychowdhury. 68-75 [doi]
- An application-aware heterogeneous prioritization framework for NoC based chip multiprocessorsTejasi Pimpalkhute, Sudeep Pasricha. 76-83 [doi]
- Adding virtualization support in MIPS 4Kc-based MPSoCsAlexandra Aguiar, Carlos Moratelli, Marcos Sartori, Fabiano Hessel. 84-90 [doi]
- HELIX: Design and synthesis of hybrid nanophotonic application-specific network-on-chip architecturesShirish Bahirat, Sudeep Pasricha. 91-98 [doi]
- An analytical approach to system-level variation analysis and optimization for multi-core processorChenyun Pan, Saibal Mukhopadhyay, Azad Naeemi. 99-106 [doi]
- Heterogeneity exploration for peak temperature reduction on multi-core platformsTianyi Wang, Ming Fan, Gang Quan, Shangping Ren. 107-114 [doi]
- Efficient post-silicon validation via segmentation of process variation envelope - Global vs local variationsPrasanjeet Das, Sandeep K. Gupta. 115-122 [doi]
- Protection of Muller-Pipelines from transient faultsSyed Rameez Naqvi, Jakob Lechner, Andreas Steininger. 123-131 [doi]
- Runtime fault recovery protocol for NoC-based MPSoCsEduardo Wächter, Augusto Erichsen, Leonardo Juracy, Alexandre M. Amory, Fernando Moraes. 132-139 [doi]
- Concurrency-oriented SoC re-certification by reusing block-level test vectorsHsuan-Ming Chou, Hong-Chang Wu, Yi-Chiao Chen, Shih-Chieh Chang. 140-147 [doi]
- Efficient trace signal selection using augmentation and ILP techniquesKamran Rahmani, Prabhat Mishra, Sandip Ray. 148-155 [doi]
- Directed test generation for hybrid systemsSudhi Proch, Prabhat Mishra. 156-162 [doi]
- Temperature-aware runtime power management for chip-multiprocessors with 3-D stacked cacheKyungsu Kang, Giovanni De Micheli, Seunghan Lee, Chong-Min Kyung. 163-170 [doi]
- Efficient region-aware P/G TSV planning for 3D ICsSong Yao, Xiaoming Chen, Yu Wang 0002, Yuchun Ma, Yuan Xie, Huazhong Yang. 171-178 [doi]
- 3D-ICs with self-healing capability for thermal effects in RF circuitsAbhilash Goyal, Madhavan Swaminathan, Abhijit Chatterjee. 179-183 [doi]
- Comparative analysis of clock distribution networks for TSV-based 3D IC designsMir Mohammad Navidi, Gyung-Su Byun. 184-188 [doi]
- Delay and power optimization with TSV-aware 3D floorplanningMohammad A. Ahmed, Malgorzata Chrzanowska-Jeske. 189-196 [doi]
- Runtime 3-D stacked cache data management for energy minimization of 3-D chip-multiprocessorsSeunghan Lee, Kyungsu Kang, Jongpil Jung, Chong-Min Kyung. 197-204 [doi]
- Statistical methodology for modeling non-IID memory fails eventsSabine Francis, Rouwaida Kanj, Rajiv V. Joshi, Ayman I. Kayssi, Ali Chehab. 205-211 [doi]
- Automated Shmoo data analysis: A machine learning approachWei Wang. 212-218 [doi]
- Double patterning-aware detailed routing with mask usage balancingSeong-I. Lei, Chris Chu, Wai-Kei Mak. 219-223 [doi]
- Design of radiation hardened wide tuning range CMOS oscillatorsSharayu Jagtap, R. Sivaramakrishna, Shalabh Gupta. 224-229 [doi]
- Computer simulation of radiation-induced clock-perturbation in phase-locked loop with analog behavioral modelTomohiro Fujita, SinNyoung Kim, Hidetoshi Onodera. 230-235 [doi]
- Measuring SET pulsewidths in logic gates using digital infrastructureVaradan Savulimedu Veeravalli, Andreas Steininger, Ulrich Schmid. 236-242 [doi]
- Fast, accurate variation-aware path timing computation for sub-threshold circuitsYanqing Zhang, Benton H. Calhoun. 243-248 [doi]
- An improved logical effort model and framework applied to optimal sizing of circuits operating in multiple supply voltage regimesXue Lin, Yanzhi Wang, Shahin Nazarian, Massoud Pedram. 249-256 [doi]
- Sub-threshold custom standard cell library validationBo Liu, Maryam Ashouei, Tobias Gemmeke, José Pineda de Gyvez. 257-262 [doi]
- Power- and area-efficient Approximate Wallace Tree Multiplier for error-resilient systemsKartikeya Bhardwaj, Pravin S. Mane, Jörg Henkel. 263-269 [doi]
- Predictive synchronization for DVFS-enabled multi-processor systemsMark Buckler, Wayne Burleson. 270-275 [doi]
- Ring-based sharing fabric for efficient pipelining of kernel-stream on CGRA-based multi-core architectureHeesun Kim, Seungyun Sohn, Yoonjin Kim. 276-283 [doi]
- Multi-core partitioned scheduling for fixed-priority periodic real-time tasks with enhanced RBoundMing Fan, Qiushi Han, Gang Quan, Shangping Ren. 284-291 [doi]
- Minimizing clock domain crossing in Network on Chip interconnectParag Kulkarni, Puneet Gupta, Rudy Beraha. 292-299 [doi]
- Optimal reliability-constrained overdrive frequency selection in multicore systemsAndrew B. Kahng, Siddhartha Nath. 300-308 [doi]
- RTL datapath optimization using system-level transformationsSamaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi. 309-316 [doi]
- Dual-sided doped memristor and it's SPICE modelling for improved electrical propertiesAnup Shrivastava, Jawar Singh. 317-322 [doi]
- Linearly separable pattern classification using memristive crossbar circuitsKomal Singh, Chitrakant Sahu, Jawar Singh. 323-329 [doi]
- Low-power programmable-logic cell arrays using nonvolatile complementary atom switchMakoto Miyamura, Toshitsugu Sakamoto, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada. 330-334 [doi]
- Volume accumulated double gate junctionless MOSFETs for low power logic technology applicationsMukta Singh Parihar, Abhinav Kranti. 335-340 [doi]
- Stack sizing analysis and optimization for FinFET logic cells and circuits operating in the sub/near-threshold regimeXue Lin, Yanzhi Wang, Massoud Pedram. 341-348 [doi]
- A parallel clustering algorithm for placementAmir Momeni, Perhaad Mistry, David Kaeli. 349-356 [doi]
- An optimization algorithm for simultaneous routing and buffer insertion with delay-power constraints in VLSI layout designC. Uttraphan, Nasir Shaikh-Husin, Mohamed Khalil Hani. 357-364 [doi]
- Kriging bootstrapped neural network training for fast and accurate process variation analysisOghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos. 365-372 [doi]
- Impedance modeling of the intracortical microelectrode for a reliable design of a brain activity recording systemDaniela De Venuto, Peter Ledochowitsch, Michel Maharabitz, Jan Rabaey. 380-385 [doi]
- Direct finite-element-based solver for 3D-IC thermal analysis via H-matrix representationYing-Chi Li, Sheldon. X.-D. Tan, Tan Yu, Xin Huang, Ngai Wong. 386-391 [doi]
- Compiler-directed leakage energy reduction for instruction scratch-pad memoriesYijie Huangfu, Wei Zhang. 392-399 [doi]
- A framework for MPSoC generation and distributed applications evaluationGuilherme M. Castilhos, Eduardo Wächter, Guilherme A. Madalozzo, Augusto Erichsen, Thiago Monteiro, Fernando Moraes. 408-411 [doi]
- Architecture for monitoring SET propagation in 16-bit Sklansky adderVaradan Savulimedu Veeravalli, Andreas Steininger. 412-419 [doi]
- Towards more reliable embedded systems through a mechanism for monitoring driver devices communicationRafael M. Madeira, Edna Barros, Camila Ascendina. 420-427 [doi]
- Experimental validation of minimum operating-voltage-estimation for low supply voltage circuitsTakashi Sato, Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi. 428-433 [doi]
- Application of six-sigma DMAIC methodology in the evaluation of test effectiveness: A case study for EDA toolsEman El Mandouh. 434-441 [doi]
- Systematic analyses for latching probability of single-event transientsHoda Pahlevanzadeh, Qiaoyan Yu. 442-449 [doi]
- Assessment of reliability impact on GHz processors with moderate overdriveMitsuhiko Igarashi, Hideki Aono, Hideaki Abe, Koji Shibutani, Kan Takeuchi. 456-460 [doi]
- Study of IC aging on ring oscillator physical unclonable functionsDinesh Ganta, Leyla Nazhandali. 461-466 [doi]
- Circuit-level approach to improve the temperature reliability of Bi-stable PUFsDinesh Ganta, Leyla Nazhandali. 467-472 [doi]
- Degradation analysis of datapath logic subblocks under NBTI aging in FinFET technologyHalil Kukner, Moustafa Khatib, Sebastien Morrison, Pieter Weckx, Praveen Raghavan, Ben Kaczer, Francky Catthoor, Liesbet Van der Perre, Rudy Lauwereins, Guido Groeseneken. 473-479 [doi]
- Fine grained wearout sensing using metastability resolution timeVikram B. Suresh, Wayne P. Burleson. 480-483 [doi]
- Asymmetric aging of clock networks in power efficient designsSenthil Arasu, Mehrdad Nourani, Frank Cano, John M. Carulli, Vijay Reddy. 484-486 [doi]
- Methodology to optimize critical node separation in hardened flip-flopsSandeep Shambhulingaiah, Srivatsan Chellappa, Sushil Kumar, Lawrence T. Clark. 486-490 [doi]
- Post-silicon tunable clock buffer allocation based on fast chip yield computationHyungjung Seo, Taewhan Kim. 490-495 [doi]
- Timing margin recovery with flexible flip-flop timing modelAndrew B. Kanng, Hyein Lee. 496-503 [doi]
- NOLO: A no-loop, predictive useful skew methodology for improved timing in IC implementationTuck Boon Chan, Andrew B. Kahng, Jiajia Li. 504-509 [doi]
- Constructing small-signal equivalent impedances using ellipsoidal normsSandeep Koranne. 510-516 [doi]
- Sense Amplifier Pass Transistor Logic for energy efficient and DPA-resistant AES circuitMehrdad Khatir, Leyla Nazhandali. 517-522 [doi]
- Assessing uniqueness and reliability of SRAM-based Physical Unclonable Functions from silicon measurements in 45-nm bulk CMOSHidehiro Fujiwara, Makoto Yabuuchi, Koji Nii. 523-528 [doi]
- TASSER: A temperature-aware statistical soft-error-rate analysis framework for combinational circuitsSung S.-Y. Hsueh, Ryan H.-M. Huang, Charles H.-P. Wen. 529-534 [doi]
- PETS: Power and energy estimation tool at system-levelSanthosh Kumar Rethinagiri, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Rabie Ben Atitallah, Smaïl Niar. 535-542 [doi]
- Impact of FinFET technology for power gating in nano-scale designKeunwoo Kim, Rouwaida Kanj, Rajiv V. Joshi. 543-547 [doi]
- Avoiding unnecessary write operations in STT-MRAM for low power implementationRajendra Bishnoi, Fabian Oboril, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori. 548-553 [doi]
- A workload-aware-design of 3D-NAND flash memory for enterprise SSDsChao Sun, Ayumi Soga, Takahiro Onagi, Koh Johguchi, Ken Takeuchi. 554-561 [doi]
- Statistical process variation analysis of a graphene FET based LC-VCO for WLAN applicationsMd. Abir Khan, Saraju P. Mohanty, Elias Kougianos. 569-574 [doi]
- An efficient semi-analytical current source model for FinFET devices in near/sub-threshold regime considering multiple input switching and stack effectTiansong Cui, Shuang Chen, Yanzhi Wang, Shahin Nazarian, Massoud Pedram. 575-581 [doi]
- Assertion-based verification for system-level designsHasan Sohofi, Zainalabedin Navabi. 582-588 [doi]
- Coverage of compositional property sets under reactive constraintsBinghao Bao, Jörg Bormann, Markus Wedler, Dominik Stoffel, Wolfgang Kunz. 589-596 [doi]
- Automated methods for eliminating X bugsKai-Hui Chang, Yen-Ting Liu, Chris Browy. 597-603 [doi]
- Specification and formal verification of power gating in processorsAmir Masoud Gharehbaghi, Masahiro Fujita. 604-610 [doi]
- Formal verification of safety of polymorphic heterogeneous multi-core architecturesMiroslav N. Velev, Ping Gao 0002. 611-617 [doi]
- Simulation and satisfiability guided counter-example triage for RTL design debuggingZissis Poulos, Yu-Shen Yang, Andreas G. Veneris, Bao Le. 618-624 [doi]
- FastSpot: Host-compiled thermal estimation for early design space explorationDarshan Gandhi, Andreas Gerstlauer, Lizy John. 625-632 [doi]
- Maximizing throughput of power/thermal-constrained processors by balancing power consumption of coresAbhishek A. Sinkar, Hao Wang, Nam Sung Kim. 633-638 [doi]
- Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encodingPing Chi, Cong Xu, Xiaochun Zhu, Yuan Xie. 639-644 [doi]
- Thermal hotspot reduction in mm-Wave wireless NoC architecturesJacob Murray, Paul Wettin, Ryan Kim, Xinmin Yu, Partha Pratim Pande, Behrooz Shirazi, Deuk Hyoun Heo. 645-652 [doi]
- Energy-aware scratch-pad memory partitioning for embedded systemsFlorin Balasa, Noha Abuaesh, Cristian V. Gingu, Ilie I. Luican, Doru V. Nasui. 653-659 [doi]
- Energy efficient job scheduling in single-ISA heterogeneous chip-multiprocessorsYing Zhang, Lide Duan, Bin Li, Lu Peng, Sadagopan Srinivasan. 660-666 [doi]
- ULSNAP: An ultra-low power event-driven microcontroller for sensor network nodesCarlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, Rajit Manohar. 667-674 [doi]
- An energy-efficient mobile PAM memory interface for future 3D stacked mobile DRAMsMajid Jalalifar, Gyung-Su Byun. 675-680 [doi]
- Rapid prototype and implementation of a high-throughput and flexible FFT ASIP based on LISA 2.0Ting Chen, Xiaowei Pan, Hengzhu Liu, Tiebin Wu. 681-687 [doi]
- Tradeoffs between RTO and RTZ in WCHB QDI asynchronous designMatheus T. Moreira, Julian J. H. Pontes, Ney Laert Vilar Calazans. 692-699 [doi]
- Statistical analysis of process variation induced SRAM electromigration degradationZhong Guan, Malgorzata Marek-Sadowska, Sani R. Nassif. 700-707 [doi]
- Estimating true worst currents for power grid electromigration analysisDi-an Li, Malgorzata Marek-Sadowska. 708-714 [doi]
- An enlarged-partition based preconditioned iterative solver for parallel power grid simulationLe Zhang, Vivek Sarin. 715-722 [doi]
- A 3-D Fast Transform-based preconditioner for large-scale power grid analysis on massively parallel architecturesKonstantis Daloukas, Nestor E. Evmorfopoulos, Panagiota Tsompanopoulou, George I. Stamoulis. 723-730 [doi]
- On pattern generation for maximizing IR dropArunkumar Vijayakumar, Vinay C. Patil, Girish Paladugu, Sandip Kundu. 731-737 [doi]
- Design of a CMOS readout circuit for wide-temperature range capacitive MEMS sensorsYucai Wang, Vamsy P. Chodavarapu. 738-742 [doi]
- Topology optimization of a passive thermal actuatorHarald Steiner, Wilfried Hortschitz, Franz Keplinger, Thilo Sauter. 743-747 [doi]
- Thermal flow sensors based on printed circuit board technologyThilo Sauter, Thomas Glatzl, Franz Kohl, Harald Steiner, Almir Talic. 748-753 [doi]
- Realization of efficient RF energy harvesting circuits employing different matching techniqueSachin Agrawal, Sunil Kumar Pandey, Jawar Singh, Manoj Singh Parihar. 754-761 [doi]
- An integrated precision clock generator for implanted electronics with superior long-term stabilityJiyuan Luan, Michael DiVita. 762-765 [doi]