Abstract is missing.
- Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier CircuitsAmr A. R. Sayed-Ahmed, Ulrich Kühne, Daniel Große, Rolf Drechsler. 1-6 [doi]
- Hardware Verification Using Software AnalyzersRajdeep Mukherjee, Daniel Kroening, Tom Melham. 7-12 [doi]
- Equivalence Checking Using Trace PartitioningRajdeep Mukherjee, Daniel Kroening, Tom Melham, Mandayam K. Srivas. 13-18 [doi]
- Joint Circuit-System Design Space Exploration of Multiplier Unit Structure for Energy-Efficient Vector ProcessorsIvan Ratkovic, Oscar Palomar, Milan Stanic, Milovan Duric, Djordje Peic, Osman S. Unsal, Adrián Cristal, Mateo Valero. 19-26 [doi]
- A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI TechnologiesAjay Singhvi, Matheus T. Moreira, Ramy N. Tadros, Ney Laert Vilar Calazans, Peter A. Beerel. 27-32 [doi]
- Efficient Utilization of Imprecise Blocks for Hardware Implementation of a Gaussian FilterMohammad Haji Seyed Javadi, Hamid Reza Mahdiani. 33-37 [doi]
- A Detailed Routing-Aware Detailed Placement TechniqueAysa Fakheri Tabrizi, Nima Karimpour Darav, Logan M. Rakai, Andrew A. Kennings, William Swartz, Laleh Behjat. 38-43 [doi]
- An Effective Chemical Mechanical Polishing Filling ApproachChuangwen Liu, Peishan Tu, Pangbo Wu, Haomo Tang, Yande Jiang, Jian Kuang 0001, Evangeline F. Y. Young. 44-49 [doi]
- Conservatively Analyzing Transient FaultsNiels Thole, Görschwin Fey, Alberto García Ortiz. 50-55 [doi]
- Assessment of FPGA Implementations of One Sided Jacobi Algorithm for Singular Value DecompositionAli Ibrahim, Maurizio Valle, Luca Noli, Hussein Chible. 56-61 [doi]
- Index-Based Round-Robin Arbiter for NoC RoutersMasoud Oveis Gharan, Gul N. Khan. 62-67 [doi]
- VLSI Implementation of an Improved Multiplier for FFT Computation in Biomedical ApplicationsArathi Ajay, R. Mary Lourde. 68-73 [doi]
- Sub-Threshold SRAM Design in 14 Nm FinFET Technology with Improved Access Time and Leakage PowerBehzad Zeinali, Jens Kargaard Madsen, Praveen Raghavan, Farshad Moradi. 74-79 [doi]
- FPGA Based Novel High Speed DAQ System Design with Error CorrectionSwagata Mandal, Suman Sau, Amlan Chakrabarti, Jogendra Saini, Sushanta Kumar Pal, Subhasish Chattopadhyay. 80-85 [doi]
- High-Speed, Modified, Bulk stimulated, Ultra-Low-Voltage, Domino InverterAli Dadashi, Yngvar Berg, Omid Mirmotahari. 86-90 [doi]
- Modulo 2n ± 1 Fused Add-Multiply UnitsConstantinos Efstathiou, Kostas Tsoumanis, Kiamal Z. Pekmestzi, Ioannis Voyiatzis. 91-96 [doi]
- High Throughput Floating Point Exponential Function Implemented in FPGAPeter Malík. 97-100 [doi]
- Exploiting Circuit Duality to Speed up SATLuca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Maciej J. Ciesielski, Giovanni De Micheli. 101-106 [doi]
- A New Method for Defining Monotone Staircases in VLSI FloorplansBapi Kar, Susmita Sur-Kolay, Chittarnjan Mandal. 107-112 [doi]
- Logic Debugging of Arithmetic CircuitsSamaneh Ghandali, Cunxi Yu, Duo Liu, Walter Brown, Maciej J. Ciesielski. 113-118 [doi]
- Mapping DAGs on Heterogeneous Platforms Using Logic-Based Benders DecompostionAndreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros. 119-124 [doi]
- A Computational Primitive for Convolution based on Coupled Oscillator ArraysDonald M. Chiarulli, Brandon B. Jennings, Yan Fang, Andrew J. Seel, Steven P. Levitan. 125-130 [doi]
- Homomorphic Data Isolation for Hardware Trojan ProtectionM. Tarek Ibn Ziad, Amr Al-Anwar, Yousra Alkabani, M. Watheq El-Kharashi, Hassan Bedour. 131-136 [doi]
- SecX: A Framework for Collecting Runtime Statistics for SoCs with Multiple AcceleratorsRajshekar Kalayappan, Smruti R. Sarangi. 137-142 [doi]
- Low-Area Reed Decoding in a Generalized Concatenated Code Construction for PUFsMatthias Hiller, Ludwig Kurzinger, Georg Sigl, Sven Müelich, Sven Puchinger, Martin Bossert. 143-148 [doi]
- JSRAM: A Circuit-Level Technique for Trading-Off Robustness and Capacity in Cache MemoriesHamzeh Ahangari, Gulay Yalcin, Ozcan Ozturk, Osman S. Unsal, Adrián Cristal. 149-154 [doi]
- Reducing the Storage Requirements of a Set of Functional Test Sequences by Using a Background SequenceIrith Pomeranz. 155-160 [doi]
- A TMR Strategy with Enhanced Dependability Features Based on a Partial Reconfiguration FlowVictor M. Goncalves Martins, Paulo R. C. Villa, Horácio C. Neto, Eduardo Augusto Bezerra. 161-166 [doi]
- Low-Power and Low-Variability Programmable Delay Element and Its Application to Post-Silicon Skew TuningDaijiro Murooka, Yu Zhang, Qing Dong, Shigetoshi Nakatake. 167-171 [doi]
- A 10-Bit 500 MSPS Segmented DAC with Optimized Current Sources to Avoid Mismatch EffectSantanu Sarkar 0002, Swapna Banerjee. 172-177 [doi]
- An Improved Dynamic Latch Based Comparator for 8-Bit Asynchronous SAR ADCAnush Bekal, Rohit Joshi, Manish Goswami, Babu R. Singh, Ashok Srivatsava. 178-182 [doi]
- Translation Validation of Transformations of Embedded System Specifications Using Equivalence CheckingKunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar. 183-186 [doi]
- Design and Implementation of a Reversible Central Processing UnitLafifa Jamal, Hafiz Md. Hasan Babu. 187-190 [doi]
- An Algorithm Used in a Power Monitor to Mitigate Dark Silicon on VLSI ChipZhou Zhao, Ashok Srivastava, Shaoming Chen, Saraju P. Mohanty. 191-194 [doi]
- Validating SPARK: High Level Synthesis CompilerSoumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal. 195-198 [doi]
- Enabling Scaling of Advanced CMOS Technologies: A Reliability PerspectiveTanya Nigam, Andreas Kerber. 199 [doi]
- Digital Right Management for IP ProtectionJérôme Rampon, Renaud Perillat, Lionel Torres, Pascal Benoit, Giorgio Di Natale, Mario Barbareschi. 200-203 [doi]
- Development of a Layout-Level Hardware Obfuscation ToolShweta Malik, Georg T. Becker, Christof Paar, Wayne P. Burleson. 204-209 [doi]
- Reversible Denial-of-Service by Locking Gates Insertion for IP Cores Design ProtectionBrice Colombier, Lilian Bossuet, David Hély. 210-215 [doi]
- Identification of IP Control Units by State EncodingEdward Jung, Seonho Choi. 216-220 [doi]
- A Summary of Current and New Methods in Velocity Selective Recording (VSR) of Electroneurogram (ENG)John Taylor, Benjamin Metcalfe, Chris Clarke, Daniel Chew, Thomas Nielsen, Nick Donaldson. 221-226 [doi]
- Resource Optimized Processor for Real-Time Neural Activity MonitoringYannick Bornat, Adam Quotb, N. Lewis, Sylvie Renaud. 227 [doi]
- In-silico Phantom Axon: Emulation of an Action Potential Propagating Along Artificial Nerve FiberOlivier Rossel, Fabien Soulier, Serge Bernard, David Guiraud, Guy Cathébras. 228-230 [doi]
- A Simplified Phase Model for Oscillator Based ComputingYan Fang, Victor V. Yashin, Donald M. Chiarulli, Steven P. Levitan. 231-236 [doi]
- A Statistical Approach to Probe Chaos from Noise in Analog and Mixed Signal DesignsIbtissem Seghaier, Mohamed H. Zaki, Sofiène Tahar. 237-242 [doi]
- Multi-objective Optimization of Floating Point Arithmetic Expressions Using Iterative FactorizationAlireza Mahzoon, Bijan Alizadeh. 243-248 [doi]
- Architecture for Dual-Mode Quadruple Precision Floating Point AdderManish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So. 249-254 [doi]
- VLSI Design of Edge-Preserving Coding Artifacts Reduction for Display ProcessingZenghua Cheng, Xuchong Zhang, Huisheng Peng, Baolu Zhai, Hongbin Sun, Nanning Zheng. 255-261 [doi]
- A Custom Computing System for Finding Similarties in Complex NetworksChristian Brugger, Valentin Grigorovici, Matthias Jung 0001, Christian Weis, Christian de Schryver, Katharina Anna Zweig, Norbert Wehn. 262-267 [doi]
- Heterogeneous Error-Resilient Scheme for Spectral Analysis in Ultra-Low Power Wearable Electrocardiogram DevicesSoumya Basu, Pablo Garcia Del Valle, Georgios Karakonstantis, Giovanni Ansaloni, David Atienza. 268-273 [doi]
- Logic Switches Operating at the Minimum Energy of ComputingFrancesco Orfei, Luca Gammaitoni. 274-279 [doi]
- Synergistic Architecture and Programming Model Support for Approximate Micropower ComputingGiuseppe Tagliavini, Davide Rossi, Luca Benini, Andrea Marongiu. 280-285 [doi]
- Logic-in-Memory: A Nano Magnet Logic ImplementationM. Cofano, G. Santoro, Marco Vacca, D. Pala, Giovanni Causapruno, Fabrizio Cairo, Fabrizio Riente, Giovanna Turvani, Massimo Ruo Roch, Mariagrazia Graziano, Maurizio Zamboni. 286-291 [doi]
- Simscape Based Ultra-Fast Design Exploration of Graphene-Nanoelectronic SystemsShital Joshi, Elias Kougianos, Saraju P. Mohanty. 292-296 [doi]
- Reversible Logic Based Mapping of Quaternary Sequential Circuits Using QGFSOP ExpressionMozammel H. A. Khan, Himanshu Thapliyal. 297-302 [doi]
- Comparing Energy, Area, Delay Tradeoffs in Going Vertical with CMOS and Asymmetric HTFETsMoon Seok Kim, William Cane-Wissing, Jack Sampson, Suman Datta, Vijaykrishnan Narayanan, Sumeet Kumar Gupta. 303-308 [doi]
- Novel UHF Passive Rectifier with Tunnel FET DevicesDavid Cavalheiro, Francesc Moll, Stanimir Valtchev. 309-314 [doi]
- Hybrid STT/CMOS Design of an Interrupt Based Instant On/Off Mechanism for Low-Power SoCChristophe Layer, Kotb Jabeur, Laurent Becker, Bernard Dieny, Stephane Gros, Virgile Javerliac, Pierre Paoli, Fabrice Bernard-Granger. 315-320 [doi]
- Radiative Effects on MRAM-Based Non-Volatile Elementary StructuresJeremy Lopes, Gregory di Pendina, Eldar Zianbetov, Edith Beigné, Lionel Torres. 321-326 [doi]
- RRAM Reliability/Performance Characterization through Array Architectures InvestigationsCristian Zambelli, Alessandro Grossi, Piero Olivo, Christian Walczyk, Christian Wenger. 327-332 [doi]
- Single-Ended and Differential MRAMs Based on Spin Hall Effect: A Layout-Aware Design PerspectiveAhmedullah Aziz, William Cane-Wissing, Moon Seok Kim, Suman Datta, Vijaykrishnan Narayanan, Sumeet Kumar Gupta. 333-338 [doi]
- Using Multiple-Input NEMS for Parallel A/D Conversion and Image ProcessingKaisheng Ma, Nandhini Chandramoorthy, Xueqing Li, Sumeet Kumar Gupta, John Sampson, Yuan Xie 0001, Vijaykrishnan Narayanan. 339-344 [doi]
- Implementing Data Structure Using DNA: An Alternative in Post CMOS ComputingMayukh Sarkar, Prasun Ghosal. 345-349 [doi]
- An Unbalanced Area Ratio Study for High Performance Monolithic 3D Integrated CircuitsHossam Sarhan, Sebastien Thuries, Olivier Billoint, Fabien Clermidy. 350-355 [doi]
- Implementation of AES Using NVM Memories Based on Comparison FunctionJérémie Clément, Bruno Mussard, David Naccache, Lionel Torres. 356-361 [doi]
- Figure of Merits of 28nm Si Technologies for Implementing Laser Attack Resistant Security Dedicated CircuitsS. De Castro, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Jean-Max Dutertre. 362-367 [doi]
- A Similarity Based Circuit Partitioning and Trimming Method to Defend against Hardware TrojansYun Cheng, Ying Wang, Huawei Li, Xiaowei Li. 368-373 [doi]
- On-Chip Instrumentation for Runtime Verification in Deeply Embedded ProcessorsCiaran MacNamee, Donal Heffernan. 374-379 [doi]
- Statistical Analysis of Resource Usage of Embedded Systems Modeled in EAST-ADLRaluca Marinescu, Eduard Paul Enoiu, Cristina Seceleanu. 380-385 [doi]
- A Novel Architectural Pattern to Support the Development of Human-Robot Interaction (HRI) Systems Integrating Haptic Interfaces and Gesture Recognition AlgorithmsGiuseppe Airo Farulla, Ludovico Orlando Russo, Vincenzo Gallifuoco, Marco Indaco. 386-391 [doi]
- TSV Placement and Core Mapping for 3D Mesh Based Network-on-Chip Design Using Extended Kernighan-Lin PartitioningKanchan Manna, Vadapalli Shanmukha Sri Teja, Santanu Chattopadhyay, Indranil Sengupta. 392-397 [doi]
- Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCsXiaowen Chen, Zhonghai Lu, Yang Li, Axel Jantsch, Xueqian Zhao, Shuming Chen, Yang Guo, Zonglin Liu, Jianzhuang Lu, Jianghua Wan, Shuwei Sun, Shenggang Chen, Hu Chen. 398-403 [doi]
- Validating Delay Bounds in Networks on Chip: Tightness and PitfallsAlberto Saggio, Gaoming Du, Xueqian Zhao, Zhonghai Lu. 404-409 [doi]
- Optimized Use of Parallel Programming Interfaces in Multithreaded Embedded ArchitecturesArthur Francisco Lorenzon, Anderson Luiz Sartor, Márcia C. Cera, Antonio Carlos Schneider Beck. 410-415 [doi]
- The DRACON Embedded Many-Core: Hardware-Enhanced Run-Time Management Using a Network of Dedicated Control NodesDaniel Gregorek, Alberto García Ortiz. 416-421 [doi]
- Backlog Bound Analysis for Virtual-Channel RoutersXueqian Zhao, Zhonghai Lu. 422-427 [doi]
- A Timing Error Mitigation Technique for High Performance DesignsMehrnaz Ahmadi, Bijan Alizadeh, Behjat Forouzandeh. 428-433 [doi]
- RWT: Suppressing Write-Through Cost When Coherence is Not NeededHao Liu, Clement Devigne, Lucas Garcia, Quentin L. Meunier, Franck Wajsbürt, Alain Greiner. 434-439 [doi]
- Small FPGA Based Multiplication-Inversion Unit for Normal Basis Representation in GF(2m)Jeremy Metairie, Arnaud Tisserand, Emmanuel Casseau. 440-445 [doi]
- The Future of Nanoelectronics: New Materials, Architectures and DevicesHeike Riel. 446 [doi]
- Challenges and Perspectives of Nanoelectromagnetics in the THz RangeSergey A. Maksimenko, Mikhail V. Shuba, P. P. Kuzhir, K. G. Batrakov, G. Y. Slepyan. 447-449 [doi]
- Semi-Classical Modelling of the Electron Transport in Carbon Nanotubes and Graphene Nanoribbons for THz Range ApplicationsAntonio Maffucci. 450-455 [doi]
- Terahertz Applications of Carbon Nanotubes and Graphene NanoribbonsM. E. Portnoi, V. A. Saroka, R. R. Hartmann, O. V. Kibis. 456-459 [doi]
- Emerging Non-volatile Memory Technologies Exploration Flow for Processor ArchitectureSophiane Senni, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatié, Bruno Mussard. 460 [doi]
- Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAMLiuyang Zhang, Wang Kang, Youguang Zhang, Yuanqing Cheng, Lang Zeng, Jacques-Olivier Klein, Weisheng Zhao. 461-466 [doi]
- STT-MRAM-Based Strong PUF ArchitectureElena Ioana Vatajelu, Giorgio Di Natale, Lionel Torres, Paolo Prinetto. 467-472 [doi]
- Approximate Computing: An Energy-Efficient Computing Technique for Error Resilient ApplicationsKaushik Roy, Anand Raghunathan. 473-475 [doi]
- Near/Sub-Threshold Circuits and Approximate Computing: The Perfect Combination for Ultra-Low-Power SystemsJeremy Schlachter, Vincent Camus, Christian C. Enz. 476-480 [doi]
- Sub-Threshold Design and Architectural ChoicesChristian Piguet, Marc Pons, Daniel Séverac. 481-484 [doi]
- A Novel Phase-Based Low Overhead Fault Tolerance Approach for VLIW ProcessorsAnderson Luiz Sartor, Arthur Francisco Lorenzon, Luigi Carro, Fernanda Gusmão de Lima Kastensmidt, Stephan Wong, Antonio Carlos Schneider Beck. 485-490 [doi]
- On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity TransistorsHassan Ghasemzadeh, Pierre-Emmanuel Gaillardon, J. Zhang, Giovanni De Micheli, E. Sanchez, Matteo Sonza Reorda. 491-496 [doi]
- A Cellular Automata Based Fault Tolerant Approach in Designing Test Hardware for L1 Cache ModuleSaha Mousumi, Biplab K. Sikdar. 497-502 [doi]
- Diagnosis of Delay Faults Considering HazardsYoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja. 503-508 [doi]
- DONUT: A Double Node Upset Tolerant LatchNikolaos Eftaxiopoulos, Nicholas Axelos, Kiamal Z. Pekmestzi. 509-514 [doi]
- An ATPG Flow to Generate Crosstalk-Aware Path Delay PatternAnu Asokan, Alberto Bosio, Arnaud Virazel, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch. 515-520 [doi]
- Analyzing the Impact of Frequency and Diverse Path Delays in the Time Vulnerability Factor of Master-Slave D Flip-FlopsAlexandra L. Zimpeck, Fernanda Lima Kastensmidt, Ricardo Reis. 521-526 [doi]
- Using Intra-Line Level Pairing for Graceful Degradation Support in PCMsMarjan Asadinia, Hamid Sarbazi-Azad. 527-532 [doi]
- Using Configurable Bit-Width Voters to Mask Multiple Errors in Integrated CircuitsThiago Berticelli Lo, Fernanda Lima Kastensmidt, Antonio Carlos Schneider Beck. 533-538 [doi]
- Communication-Aware Parallelization Strategies for High Performance ApplicationsImran Ashraf, Koen Bertels, Nader Khammassi, Jean-Christophe Le Lann. 539-544 [doi]
- Design of Fault-Tolerant and Reliable Networks-on-ChipJunshi Wang, Masoumeh Ebrahimi, Letian Huang, Axel Jantsch, Guangjun Li. 545-550 [doi]
- Design Exploration for next Generation High-Performance Manycore On-chip Systems: Application to big.LITTLE ArchitecturesAnastasiia Butko, Abdoulaye Gamatié, Gilles Sassatelli, Lionel Torres, Michel Robert. 551-556 [doi]
- On Analysis of On-chip DC-DC Converters for Power Delivery NetworksGhizlane Mouslih, Aida Todri-Sanial, Pascal Nouet. 557-560 [doi]
- Multilevel Modeling Methodology for Reconfigurable Computing Systems Based on Silicon PhotonicsZhen Li, Sébastien Le Beux, Christelle Monat, Xavier Letartre, Ian O'Connor. 561-566 [doi]
- Multi-swarm Optimization of a Graphene FET Based Voltage Controlled Oscillator CircuitElias Kougianos, Shital Joshi, Saraju P. Mohanty. 567-572 [doi]
- Fast Stimuli Generation for Design Validation of RTL Circuits Using Binary Particle Swarm OptimizationPrateek Puri, Michael S. Hsiao. 573-578 [doi]
- On the Performance Exploration of 3D NoCs with Resistive-Open TSVsCharles Effiong, Vianney Lapotre, Abdoulaye Gamatié, Gilles Sassatelli, Aida Todri-Sanial, Khalid Latif. 579-584 [doi]
- SymmTop: A Symmetric Circuit Topology for Ultra Low Power Wide Temperature-Range ApplicationsElena K. Weinberg, Mircea R. Stan. 585-590 [doi]
- Energy-Aware Computing via Adaptive Precision under Performance Constraints in OFDM Wireless ReceiversFernando Cladera, Matthieu Gautier, Olivier Sentieys. 591-596 [doi]
- The Solar Cells and the Battery Charger System Using the Fast and Precise Analog Maximum Power Point Tracking CircuitsYasuhiro Sugimoto. 597-602 [doi]
- 3D DFT Challenges and SolutionsYassine Fkih, Pascal Vivet, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, Juergen Schloeffel. 603-608 [doi]
- Thermal Aspects and High-Level Explorations of 3D Stacked DRAMsChristian Weis, Matthias Jung 0001, Omar Naji, Norbert Wehn, Cristiano Santos, Pascal Vivet, Andreas Hansson. 609-614 [doi]
- Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache InterconnectsPascal Vivet, Christian Bernard, Eric Guthmuller, Ivan Miro Panades, Yvain Thonnart, Fabien Clermidy. 615-620 [doi]
- A Framework for Efficient Implementation of Analog/RF Alternate Test with Model RedundancySyhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell. 621-626 [doi]
- Test and Calibration of RF Circuits Using Built-in Non-intrusive SensorsAthanasios Dimakos, Martin Andraud, Louay Abdallah, Haralampos-S. Stratigopoulos, Emmanuel Simeu, Salvador Mir. 627 [doi]
- Silicon Demonstration of Statistical Post-Production TuningYichuan Lu, Kiruba Subramani, He Huang, Nathan Kupp, Yiorgos Makris. 628-633 [doi]
- Toward Adaptation of ADCs to Operating Conditions through On-chip CorrectionVincent Kerzerho, Ludovic Guillaume-Sage, Florence Azaïs, Mariane Comte, Michel Renovell, Serge Bernard. 634-639 [doi]
- A Full-Swing CMOS Current Steering DAC with an Adaptive Cell and a Quaternary DriverYanghyeok Choi, Seonghyun Park, Jieun Yoo, Seol Namgung, Minkyu Song. 640-645 [doi]
- Flexible Ultra-Low-Voltage CMOS Circuit Design Applicable for Digital and Analog Circuits Operating below 300mVYngvar Berg, Omid Mirmotahari. 646-651 [doi]
- A Linear Comparator-Based Fully Digital Delay ElementAfshin Seraj, Mohammad Maymandi-Nejad, Parvin Bahmanyar, Manoj Sachdev. 652-655 [doi]
- Built-In Self Optimization for Variation Resilience of Analog FiltersJiafan Wang, Congyin Shi, Edgar Sánchez-Sinencio, Jiang Hu. 656-661 [doi]