| 169 | -- | 0 | Rajesh Gupta. From the EIC: The next EDA challenge - Design for manufacturability |
| 173 | -- | 174 | Vishwani D. Agrawal. 1985 to 1987: My years with D&T |
| 175 | -- | 176 | Carol Stolicny, Mustapha Slamani, Fidel Muradali, Geir Eide, Mike Li. ITC 2003 panels: Part 2 |
| 177 | -- | 182 | Yervant Zorian, Dimitris Gizopoulos, Cary Vandenberg, Philippe Magarshack. Guest Editors Introduction: Design for Yield and Reliability |
| 183 | -- | 191 | Juan Antonio Carballo, Sani R. Nassif. Impact of Design-Manufacturing Interface on SoC Design Methodologies |
| 192 | -- | 199 | Alessandra Nardi, Alberto L. Sangiovanni-Vincentelli. Logic Synthesis for Manufacturability |
| 200 | -- | 207 | Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian. SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure |
| 208 | -- | 215 | Davide Appello, Alessandra Fudoli, Katia Giarda, Vincenzo Tancorre, Emil Gizdarski, Ben Mathew. Understanding Yield Losses in Logic Circuits |
| 216 | -- | 227 | Melvin A. Breuer, Sandeep K. Gupta, T. M. Mak. Defect and Error Tolerance in the Presence of Massive Numbers of Defects |
| 228 | -- | 240 | Subhasish Mitra, Wei-Je Huang, Nirmal R. Saxena, Shu-Yi Yu, Edward J. McCluskey. Reconfigurable Architecture for Autonomous Self-Repair |
| 241 | -- | 247 | T. M. Mak, Angela Krstic, Kwang-Ting (Tim) Cheng, Li-C. Wang. New Challenges in Delay Testing of Nanometer, Multigigahertz Designs |
| 248 | -- | 258 | Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi. DFT for Delay Fault Testing of High-Performance Digital Circuits |
| 259 | -- | 260 | Luciano Lavagno. DAC Highlights |
| 264 | -- | 0 | Hans A. R. Manhaeve. Current testing for nanotechnologies: Myths, facts, and figures |