Journal: IEEE Design & Test of Computers

Volume 21, Issue 6

457 -- 0Rajesh K. Gupta. Verification synergies
461 -- 463Carl Pixley, Sharad Malik. Guest Editors Introduction: Exploring Synergies for Design Verification
464 -- 471Martin Zambaldi, Wolfgang Ecker, Renate Henftling, Matthias Bauer. A Layered Adaptive Verification Platform for Simulation, Test, and Emulation
472 -- 482Serdar Tasiran, Yuan Yu, Brannon Batson. Linking Simulation with Formal Verification at a Higher Level
484 -- 493Young-Il Kim, Chong-Min Kyung. TPartition: Testbench Partitioning for Hardware-Accelerated Functional Verification
494 -- 502Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir. Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation
504 -- 512Shuo Sheng, Michael S. Hsiao. Success-Driven Learning in ATPG for Preimage Computation
514 -- 523Ioannis Papaefstathiou. Titan II: An IPcomp Processor for 10-Gbps Networks
524 -- 535Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli. On-Chip Self-Calibrating Communication Techniques Robust to Electrical Parameter Variations
536 -- 543Marcel A. Kossel, Martin L. Schmatz. Jitter Measurements of High-Speed Serial Links
544 -- 551Glenn H. Chapman, Sunjaya Djaja, Desmond Y. H. Cheung, Yves Audet, Israel Koren, Zahava Koren. A Self-Correcting Active Pixel Sensor Using Hardware and Software Correction
552 -- 562Fernanda Lima Kastensmidt, Gustavo Neuberger, Renato Fernandes Hentschke, Luigi Carro, Ricardo Reis. Designing Fault-Tolerant Techniques for SRAM-Based FPGAs
563 -- 571Naran Sirisantana, Bipul Chandra Paul, Kaushik Roy. Enhancing Yield at the End of the Technology Roadmap
572 -- 586Ikhwan Lee, Yongseok Choi, Youngjin Cho, Yongsoo Joo, Hyeonmin Lim, Hyung Gyu Lee, Hojun Shim, Naehyuck Chang. Web-Based Energy Exploration Tool for Embedded Systems
590 -- 591. Book Reviews
592 -- 593Victor Berman. System-level design language standard needed
594 -- 595Vladimir Hahanov, Raimund Ubar, Subhasish Mitra. Conference Reports
596 -- 0. DATC Newsletter
608 -- 0Scott Davidson. Design illiteracy

Volume 21, Issue 5

345 -- 0Rajesh Gupta. Silicon for embedded multimedia processing
350 -- 353. Conference Reports
354 -- 356Radu Marculescu, Petru Eles. Guest Editors Introduction: Designing Real-Time Embedded Multimedia Systems
358 -- 366Chaeseok Im, Soonhoi Ha. Energy Optimization for Latency- and Quality-Constrained Video Applications
368 -- 377Alexander Maxiaguine, Samarjit Chakraborty, Simon Künzli, Lothar Thiele. Evaluating Schedulers for Multimedia Processing on Buffer-Constrained SoC Platforms
378 -- 387Paul Marchal, Francky Catthoor, Davide Bruni, Luca Benini, José Ignacio Gómez, Luis Piñuel. Integrated Task Scheduling and Data Assignment for SDRAMs in Dynamic Applications
388 -- 396Hojun Shim, Naehyuck Chang, Massoud Pedram. A Backlight Power Management Framework for Battery-Operated Multimedia Systems
398 -- 405Sudeep Pasricha, Manev Luthra, Shivajit Mohapatra, Nikil D. Dutt, Nalini Venkatasubramanian. Dynamic Backlight Adaptation for Low-Power Handheld Devices
406 -- 415Haris Lekatsas, Jörg Henkel, Srimat T. Chakradhar, Venkata Jakkula. Cypress: Compression and Encryption of Data and Code for Embedded Multimedia Systems
416 -- 428Maria Varsamou, Nikolaos Papandreou, Theodore Antonakopoulos. From Protocol Models to Their Implementation: A Versatile Testing Methodology
430 -- 440A. J. van de Goor. An Industrial Evaluation of DRAM Tests
441 -- 446. Engineering Applied to Societal Problems: A New Outlook
448 -- 449Scott Davidson. A practical look at ATPG
450 -- 451Erich Marschner, Victor Berman. The continuing evolution of EDA standards
455 -- 0. DATC Newsletter
456 -- 0Scott Davidson. Open-source hardware

Volume 21, Issue 4

269 -- 270. From the EIC: Manufacturing test woes
274 -- 276André Ivanov, Fabrizio Lombardi, Cecilia Metra. Guest Editors Introduction: Advances in VLSI Testing at MultiGbps Rates
278 -- 286T. M. Mak, Mike Tripp, Anne Meixner. Testing Gbps Interfaces without a Gigahertz Tester
288 -- 301David C. Keezer, Dany Minier, Marie-Christine Caron. Multiplexing ATE Channels for Production Testing at 2.5 Gbps
302 -- 313Nelson Ou, Touraj Farahmand, Andy Kuo, Sassan Tabatabaei, André Ivanov. Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects
314 -- 321Stephen K. Sunter, Aubin Roy. On-Chip Digital Jitter Measurement, from Megahertz to Gigahertz
322 -- 330Ming-Jun Hsiao, Jing-Reng Huang, Tsin-Yuan Chang. A Built-In Parametric Timing Measurement Unit
331 -- 338Debesh K. Das, Hideo Fujiwara, Yungang Li, Yinghua Min, Shiyi Xu, Yervant Zorian. Design & Test Education in Asia
339 -- 341. Conference Reports
342 -- 0. Panel Summaries
343 -- 0John Willis, Joe Damore. Design automation Technical Committee Newsletter
344 -- 0Rob Aitken. Test at Gbps: Megaproblem or micromanagement?

Volume 21, Issue 3

169 -- 0Rajesh Gupta. From the EIC: The next EDA challenge - Design for manufacturability
173 -- 174Vishwani D. Agrawal. 1985 to 1987: My years with D&T
175 -- 176Carol Stolicny, Mustapha Slamani, Fidel Muradali, Geir Eide, Mike Li. ITC 2003 panels: Part 2
177 -- 182Yervant Zorian, Dimitris Gizopoulos, Cary Vandenberg, Philippe Magarshack. Guest Editors Introduction: Design for Yield and Reliability
183 -- 191Juan Antonio Carballo, Sani R. Nassif. Impact of Design-Manufacturing Interface on SoC Design Methodologies
192 -- 199Alessandra Nardi, Alberto L. Sangiovanni-Vincentelli. Logic Synthesis for Manufacturability
200 -- 207Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian. SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure
208 -- 215Davide Appello, Alessandra Fudoli, Katia Giarda, Vincenzo Tancorre, Emil Gizdarski, Ben Mathew. Understanding Yield Losses in Logic Circuits
216 -- 227Melvin A. Breuer, Sandeep K. Gupta, T. M. Mak. Defect and Error Tolerance in the Presence of Massive Numbers of Defects
228 -- 240Subhasish Mitra, Wei-Je Huang, Nirmal R. Saxena, Shu-Yi Yu, Edward J. McCluskey. Reconfigurable Architecture for Autonomous Self-Repair
241 -- 247T. M. Mak, Angela Krstic, Kwang-Ting (Tim) Cheng, Li-C. Wang. New Challenges in Delay Testing of Nanometer, Multigigahertz Designs
248 -- 258Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi. DFT for Delay Fault Testing of High-Performance Digital Circuits
259 -- 260Luciano Lavagno. DAC Highlights
264 -- 0Hans A. R. Manhaeve. Current testing for nanotechnologies: Myths, facts, and figures

Volume 21, Issue 2

77 -- 78Rajesh Gupta. From the EIC: Past successes, future challenges
79 -- 0Roy L. Russo. Serving a growing community: How D&T began
80 -- 82Magdy S. Abadir, Li-C. Wang. Guest Editors Introduction: The Verification and Test of Complex Digital ICs
84 -- 93Allon Adir, Eli Almog, Laurent Fournier, Eitan Marcus, Michal Rimon, Michael Vinov, Avi Ziv. Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification
94 -- 101Carl Scafidi, J. Douglas Gibson, Rohit Bhatia. Validating the Itanium 2 Exception Control Unit: A Unit-Level Approach
102 -- 109Fulvio Corno, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero. Automatic Test Program Generation: A Case Study
111 -- 120Chia-Chih Yen, Jing-Yang Jou, Kuang-Chien Chen. A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation
122 -- 131Prabhat Mishra, Nikil Dutt, Narayanan Krishnamurthy, Magdy S. Abadir. A Top-Down Methodology for Microprocessor Validation
132 -- 143Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang. Safety Property Verification Using Sequential SAT and Bounded Model Checking
144 -- 156Rob Aitken, Stefan Eichenberger, Gary Maier, Sandip Kundu, Hank Walker. ITC 2003 Roundtable: Design for Manufacturability
157 -- 158Peter J. Ashenden. Policies and procedures - who needs them?
159 -- 0William Mann. Southwest Test Workshop 2004
160 -- 163Carol Stolicny, Tapio Koivukangas, Rubin A. Parekhji, Ian G. Harris, Rob Aitken. ITC 2003 panels: Part 1
164 -- 165Paolo Prinetto, Alfredo Benso. Test Technology TC Newsletter
166 -- 0John Willis, Andreas Kuehlmann. Design Automation TC Newsletter
168 -- 0Prab Varma. Verification evolution or industrial revolution?

Volume 21, Issue 1

1 -- 0Rajesh Gupta. From the Editor in Chief: Predictability in Design and Manufacturing
9 -- 12Dwight D. Hill, Andrew B. Kahng. Guest Editors Introduction: RTL to GDSII - From Foilware to Standard Practice
14 -- 22Louise Trevillyan, David S. Kung, Ruchir Puri, Lakshmi N. Reddy, Michael A. Kazda. An Integrated Environment for Technology Closure of Deep-Submicron IC Designs
24 -- 32Jinan Lou, Wei Chen. Crosstalk-Aware Placement
34 -- 43Bin-Hong Lin, Cheng-Wen Wu, Hwei-Tsu Ann Luh. Efficient and Economical Test Equipment Setup Using Procorrelation
44 -- 55Sule Ozev, Ismet Bayraktaroglu, Alex Orailoglu. Seamless Test of Digital Components in Mixed-Signal Paths
56 -- 63Naran Sirisantana, Kaushik Roy. Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses
65 -- 66Hans-Joachim Wunderlich, Sandeep K. Shukla. Panel Summaries
68 -- 0Xiaowei Li. Conference Reports
69 -- 0. Design Automation Technical Committee Newsletter
70 -- 71. Test Technology TC Newsletter
72 -- 0Scott Davidson. Paperless Design and Test