| 698 | -- | 704 | Jong Kang Park, Jong-Tae Kim. A soft error mitigation technique for constrained gate-level designs |
| 705 | -- | 710 | Jongwoo Bae, Jinsoo Cho. A decoupled architecture for multi-format decoder |
| 711 | -- | 717 | Byung Hwa Jung, Sung-Chan Kang, Jae-Hyuk Oh, Yoon-Suk Park, Yong-Ki Kim, Yonggu Kang, Jong Woo Kim, Bai-Sun Kong. Novel bootstrapped CMOS differential logic family for ultra-low voltage SoCs |
| 718 | -- | 724 | Jing-Wein Wang. T-eigenfaces selection for false face reduction |
| 725 | -- | 731 | Woo-Yong Choi, Sungju Lee, Daesung Moon, Yongwha Chung, Kiyoung Moon. A fast algorithm for polynomial reconstruction of fuzzy fingerprint vault |
| 732 | -- | 737 | Yasuhiro Yamaji, Tokihiko Yokoshima, Katsuya Kikuchi, Hiroshi Nakagawa, Masahiro Aoyagi. Chemical flip-chip bonding method for fabricating 10-µm-pad-pitch interconnect |
| 738 | -- | 743 | Shigenori Kinjo. A new MMSE channel estimation algorithm for OFDM systems |
| 744 | -- | 749 | Keivan Navi, Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Babak Mazloom Nezhad, Omid Hashemipour, K. Shams. Ultra high speed Full Adders |
| 750 | -- | 755 | Jawar Singh, Dhiraj K. Pradhan, Simon Hollis, Saraju P. Mohanty. A single ended 6T SRAM cell design for ultra-low-voltage applications |
| 756 | -- | 761 | Ichiro Ruiz Obregon, Alberto Palacios Pawlovsky. A hybrid SA-EA method for finding the maximum number of switching gates in a combinational circuit |
| 762 | -- | 768 | Chun-Hua Cheng, Shih-Hsu Huang, Wen-Pin Tu. Module binding for low power clock gating |
| 769 | -- | 775 | Hua-Pin Chen, Pao-Lung Chu. Versatile voltage-mode multifunction biquadratic filter employing DDCCs |
| 776 | -- | 781 | Hiroki Goto, Masato Yoshida, Tatsunori Omiya, Keisuke Kasai, Masataka Nakazawa. Polarization and frequency division multiplexed 1Gsymbol/s, 64 QAM coherent optical transmission with 8.6bit/s/Hz spectral efficiency over 160km |