| 0 | -- | 0 | Kurt P. Judmann. Chairman's introduction |
| 0 | -- | 0 | Antonio Núñez. Program chairman's introduction |
| 1 | -- | 0 | . Session K1: Opening and keynote session |
| 5 | -- | 0 | . Session K2: Keynote session |
| 9 | -- | 0 | . Session K3: Keynote session |
| 11 | -- | 0 | . Session A1: Topics on computer architecture |
| 13 | -- | 21 | Manuel Lois Anido. Improving the division instruction of application-specific RISCs |
| 23 | -- | 28 | Edil S. T. Fernandes, Valmir C. Barbosa, Alberto Ferreira de Souza, Nelson Q. Vasconcelos. Micro-instruction placement by simulated annealing |
| 29 | -- | 36 | B. W. Watson, Willem J. Withagen, M. P. J. Stevens. Compilation techniques for a high level language processor |
| 37 | -- | 0 | . Session A2: Multiprocessor |
| 39 | -- | 43 | Samir Bouaziz, Edwige E. Pissaloux, Alain Mérigot, Francis Devos. A communication mechanism and its implementation in the Multi-SIMD massively parallel machine SPHINX |
| 45 | -- | 52 | Júlio Salek Aude, A. J. O. Cruz, Ageu Cavalcanti Pacheco Jr., Alexandre Malheiros Meslin, Gerson Bronstein, G. P. Azevedo, N. R. Figueira, R. P. Azevedo, S. C. Oliveira. MULTIPLUS: A modular high-performance multiprocessor |
| 53 | -- | 58 | Rafael Dueire Lins. A shared memory architecture for parallel cyclic reference counting |
| 59 | -- | 60 | . Session A3: Optimization of high speed digital circuits |
| 61 | -- | 68 | Luis Ferragut, Rafael Montenegro, G. Winter, A. Núñez. Accurate extraction of interconnect capacitances by adaptive mixed F.E.M |
| 69 | -- | 73 | Veronika Eisele, Doris Schmitt-Landsiedel. Optimization and architectural evaluation of regular combinatoric structures |
| 75 | -- | 82 | K. Eshraghian, R. Sarmiento, P. P. Carballo, A. Núñez. Speed-area-power optimization for DCFL and SDCFL class of logic using ring notation |
| 83 | -- | 84 | . Session A4: Object orientied VLSI design |
| 85 | -- | 92 | Wlodzimierz Wrona, Adam Pawlak. VLSI integrated circuit design representation in an object-oriented CAD environment |
| 93 | -- | 100 | Colin C. Charlton, Paul H. Leng, Mark Rivers. Object-oriented modelling in digital circuit CAD systems |
| 101 | -- | 108 | Yun-Chao Hu, Ad Verschueren, M. P. J. Stevens. Object oriented system analysis for VLSI |
| 109 | -- | 0 | . Session B1: Design and testing of real-time systems |
| 111 | -- | 118 | J. S. Sagoo, D. J. Holding. A comparison of temporal Petri net techniques in the specification and design of hard real-time systems |
| 119 | -- | 126 | Peng Tu, Kwei-Jay Lin. Minimizing the maximum lateness in real-time computations with extended deadlines |
| 127 | -- | 134 | Hannu Honka, Matti Kattilakoski. A simulation-based system for testing real-time embedded software in the host environment |
| 137 | -- | 144 | Fred Hemery, Dominique Lazure, Eric Delattre, Jean-François Méhaut. An analysis of communication and multiprogramming in the Helios operating system |
| 145 | -- | 152 | Shang-Rong Tsai, Ru Jing Chen. Interprocess communication with multicast support in DMINIX operating system |
| 153 | -- | 160 | Franck Delaplace, Jean-Louis Giavillo. An efficient routing strategy to support process migration |
| 161 | -- | 0 | . Session B3: Hardware building block |
| 163 | -- | 169 | R. Rauscher, V. Grupe. Use of mathematical procedures for the task of power measurement and the corresponding VLSI-realization |
| 171 | -- | 177 | Jean-Luc Béchennec, Franck Cappello, Daniel Etiemble. 3D hardware packages for parallel architectures |
| 179 | -- | 181 | Jean-Luc Peter. Design of a custom dram storage unit coupled to i486(tm) |
| 183 | -- | 0 | . Session B4: VLSI synthesis |
| 185 | -- | 192 | J. Septiéna, Daniel Mozos, Román Hermida, Francisco Tirado. A hardware allocator guided by cost functions |
| 193 | -- | 198 | H.-G. Haeck, F. Krohm, Yiannos Manoli. Data path synthesis from a microcontroller instruction set specification in microsyn |
| 199 | -- | 206 | Jordi Cortadella, Rosa M. Badia, Eduard Ayguadé. Scheduling in a continuous area-time design space |
| 207 | -- | 0 | . Session C1: CMOS implementation of the IBM ESA/390 |
| 209 | -- | 214 | Nicholas Roethe, Udo Wille. A CMOS implementation of the ESA/390 mainframe architecture |
| 215 | -- | 219 | Gerhard Döttling. Data consistency in a multiprocessor system with 'store in' cache concept |
| 221 | -- | 226 | Dietmar Schmunkamp. The clock, test and maintenance control chip of the IBM ES/9221 |
| 227 | -- | 234 | A. Tietz, J. Koehl. A VLSI - CAD system for efficient design of CMOS/390 processors |
| 237 | -- | 241 | Mario Dal Cin. Fault tolerance for highly parallel computers |
| 243 | -- | 252 | V. Lakshmi Narasimhan, Tom Downs. Fault tolerant aspects of a dynamic dataflow architecture - PATTSY |
| 253 | -- | 259 | Andreas Steininger, Herbert Schweinzer. Towards an optimal combination of error detection mechanisms |
| 261 | -- | 0 | . Session C3: Advances in object oriented design |
| 263 | -- | 270 | Massimo Ancona, Gabriele Nani, Maddali Paci. An object oriented approach to data persistence |
| 271 | -- | 279 | Alexander Schill. Language and runtime support for distributed object groups |
| 281 | -- | 288 | K. C. Huang, W. S. Hsieh, C.-S. Lu, M. S. Yang, T. S. Nain, Ihnen Lin. Implementation and design of PVD: An interactive protocol specification and validation environment |
| 289 | -- | 296 | A. T. Balou, Apostolos Nikolaos Refenes. The design and implementation of VOOM: a parallel virtual Object Oriented machine |
| 297 | -- | 0 | . Session C4: Architectural Synthesis |
| 299 | -- | 306 | Manfred Schäfer, Georg Klein-Heßling. A design concept for verified concurrent controllers |
| 307 | -- | 313 | Panagiotis Tsanakas, George K. Papakonstantinou, Stefanos Kaxiras. A Prolog-based design environment for the high-level synthesis of application-specific architectures |
| 315 | -- | 321 | Stefano Antoniazzi, Mirella Mastretti. An architectural design support environment for high-performance digital systems |
| 323 | -- | 331 | L. P. M. Benders, M. P. J. Stevens. Task level behavioral hardware description |
| 335 | -- | 341 | Jürgen Büddefeld, Karl-Erwin Grosspietsch, Bedrich J. Hosticka, Roland Klinkel, G. Wagner. An intelligent sensor integrated preprocessing facility for neural networks |
| 343 | -- | 348 | V. Silva, L. Cruz, F. Lopes, A. Rodrigues, L. de Sá. Multiprocessor based image coding |
| 349 | -- | 355 | Cesare Alippi. The determination of angular values and parameters in flat surfaces: from the mathematical approach to the CORDIC architecture |
| 357 | -- | 0 | . Session D2: Fault tolerant parallel software |
| 359 | -- | 363 | Gilles Muller, Bruno Rochat, Patrick Sanchez. A stable transactional memory for building robust object oriented programs |
| 365 | -- | 372 | . Session D2: Fault tolerant parallel software |
| 373 | -- | 380 | . Session D2: Fault tolerant parallel software |
| 381 | -- | 0 | . Session D3: Program development environments |
| 383 | -- | 391 | S. El-Kassas. Visual languages their definition and applications in system development |
| 393 | -- | 400 | Valmir C. Barbosa, Lúcia Maria de A. Drummond, Astrid Luise H. Hellmuth. An integrated software environment for large-scale Occam programming |
| 401 | -- | 409 | Miguel Angel Ruz Fernández, Gonzalo León Serrano, María Victoria Elbal Díaz. An integrated framework for the design of distributed programming environments |
| 411 | -- | 0 | . Session D4: VLSI design and routing |
| 413 | -- | 415 | Fermín Calvo Torre. From a high level description of an IC to silicium: Don't loose design intent |
| 417 | -- | 423 | Michal Servít, Jan Schmidt. Strategy of one and half layer routing |
| 425 | -- | 433 | N. A. Kyrloglou, S. Koutroubinas, A. Koyandis, Constantinos E. Goutis. A placing and routing tool implemented in Prolog |
| 435 | -- | 0 | . Session E1: Image recognition |
| 437 | -- | 446 | Apostolos Nikolaos Refenes, Cesare Alippi. Iiistological image understanding by error backpropagation |
| 447 | -- | 452 | Jukka Neejärvi, Viktor Fischer, Sakari Alenius, Yrjö Neuvo. Knowledge-based segmentation using morphological filters |
| 453 | -- | 460 | Roberto Jezieniecki, Eduardo Rovaris. An image distance measure insensitive to amplitude and mean value variations: Application to data reduction through SVD |
| 461 | -- | 0 | . Session E2: Parallel program development |
| 463 | -- | 470 | Theo Ungerer. Parallelising C++-programs for transputer systems |
| 471 | -- | 478 | Péter Kacsuk. Implementing Prolog on a DAP/Multi-transputer computer |
| 479 | -- | 486 | Emilio Luque, Remo Suppi, Joan Sorribes, M. A. Mayosky, Miquel A. Senar. Simulation and visualization tools for link-based parallel architectures |
| 487 | -- | 0 | . Session E3: Prolog |
| 489 | -- | 496 | H. Sorensen, T. A. Delaney, W. P. Kenneally, S. J. M. Murphy, F. B. O'Flaherty, A. B. O'Mahony, D. M. J. Power. Towards a development environment for fifth generation systems |
| 497 | -- | 504 | Gilles Berger-Sabbatel, Abderrazak Jemai. Prolog on a RISC: Implementation and evaluation |
| 505 | -- | 514 | Hendrik C. R. Lock, Anamaria Martins. Issues in the implementation of Prolog, and their optimization |
| 515 | -- | 0 | . Session E4: Hardware description languages |
| 517 | -- | 524 | Roy D. Dowsing, R. Elliott. A higher level of behavioural specification: An example in interval temporal logic |
| 525 | -- | 530 | József Sziray, Zsolt Nagy. Opart: A hardware-description language for test generation |
| 531 | -- | 538 | R. J. Huis in 't Veld. Formalizing the design-trajectory of sequential machines |
| 539 | -- | 0 | . Session F1: Digital signal processing |
| 541 | -- | 547 | Alois C. Knoll, Markus Freericks. An applicative real-time language for DSP-programming supporting asynchronous data-flow concepts |
| 549 | -- | 556 | Christine Dours-Senac. Temporal control improvement of hidden Markov models for automatic speech recognition |
| 557 | -- | 563 | Spiros Nikolaidis, Odysseas G. Koufopavlou, Sergios Theodoridis, Constantinos E. Goutis. Array processor for LS FIR system identification |
| 565 | -- | 572 | Kyösti Rautiola, Pekka Jokitalo. DSP-architecture design with a Petri-net-based simulator |
| 573 | -- | 0 | . Session F2: Interconnection networks for multiprocessors |
| 575 | -- | 582 | Imrich Chlamtac, Aura Ganz, Martin G. Kienzle. Control policies for interconected distributed systems via an HIPPI switch |
| 583 | -- | 587 | C. S. Yang, W. S. Hsieh, D. C. Lou, J. S. Tzeng. A regular interconnection network |
| 589 | -- | 592 | C. S. Yang, S. Y. Wu, K. C. Huang. A reconfigurable modular fault tolerant generalized Boolean n-cube network |
| 593 | -- | 599 | Gerard J. M. Smit, Paul J. M. Havinga, Pierre G. Jansen, Fokke de Boer, Bert Molenkamp. On hardware for generating routes in Kautz digraphs |
| 601 | -- | 0 | . Session F3: System design |
| 603 | -- | 608 | Franz Lehner 0001. Software life cycle management based on a phase distinction method |
| 609 | -- | 616 | Ernest Wallmüller. Software quality management |
| 617 | -- | 624 | Krzysztof Sacha. Transnet: A method for transformational development of embedded software |
| 625 | -- | 634 | Javier Miranda, José Fortes Gálvez. A modula-2-like systems programming language and its implementation |
| 637 | -- | 644 | D. Navarro, A. Roy, Michel Robert, Denis Deschacht, Daniel Auvergne. TVA: A timing verifier with analytic temporal modelling |
| 645 | -- | 650 | Thomas Müller-Wipperfürth, Hermann Hellwagner, Franz Pichler. LISAS - Simulation tool for regular networks of finite state machines |
| 651 | -- | 656 | Thomas Müller-Wipperfürth, Hermann Hellwagner, Franz Pichler. LISAS - Simulation tool for regular networks of finite state machines |
| 657 | -- | 664 | Lech Józwiak, J. C. Kolsteren. An efficient for the sequential general decomposition of sequential machines |
| 665 | -- | 0 | . Session F5: The ESPRIT-PATRICIA project |
| 667 | -- | 673 | Eleanor M. Mayger, M. D. Francis, R. L. Harris, Gerry Musgrave, Michael P. Fourman. The need for a core method DIALOG - Linking formal proof to the design environment |
| 675 | -- | 682 | M. Hadjinicolaeu, N. Burgess, Donatella Sciuto, G. Buananno, Patrizia Cavalloro, Giuseppe Zaza. The Patricia testability analysis tool |
| 683 | -- | 690 | Anna Antola, Fausto Distante. DFG: a graph based approach for algorithmic flow driven architecture synthesis |
| 691 | -- | 698 | Robert M. Zimmer, Alan J. MacDonald, Robert Holte. CAD for verified hardware design via category theory |
| 699 | -- | 700 | . Session G1: Control applications |
| 701 | -- | 708 | D. P. Kwok, P. Wang, C. K. Li. A combined fuzzy and classical PID controller |
| 709 | -- | 716 | Herbert Schweinzer, Günther Stadlbauer. A multiprocessor bus system with cyclic data exchange for the field of control and signal processing |
| 717 | -- | 719 | Raimund Mitterbauer. Concept for aelf-calibrating floatingpoint-converter for audio-applications |
| 721 | -- | 0 | . Session G2: Network communication protocols |
| 723 | -- | 730 | W. S. Hsieh, T. S. Nain, M. S. Yang, C.-S. Lu, K. C. Huang, J. R. Tseng. A fast method of protocol validation using reduced stable state exploration technique |
| 731 | -- | 738 | Monika Kapus-Kolar. Deriving protocol specifications from service specifications including parameters |
| 739 | -- | 744 | Stephen P. Van Trees, Ophir Frieder. On the specification and implementation of X.25 using CSP and OCCAM |
| 745 | -- | 0 | . Session G3: Database systems |
| 747 | -- | 754 | Jong T. Lim, Song C. Moon. Global checkpointing scheme for heterogeneous distributed database systems |
| 755 | -- | 764 | Achilles Kameas, Panagiotis Fitsilis, Georgios Pavlides. Algorithms for inference control |
| 765 | -- | 772 | Byung Y. Hwang, Byung W. Kim, Song C. Moon. Efficient access method for multi-dimensional complex objects in spatial databases: BR tree |
| 773 | -- | 0 | . Session G4: VLSI testing and modelling I |
| 775 | -- | 782 | Giacomo Buonanno, Fabrizio Lombardi, Donatella Sciuto, Y.-N. Sken. Multiple stuck-at faults detection in CMOS combinational gates |
| 783 | -- | 789 | François Darlay. Detection of multiple stuck-on/stuck-open faults by single faults test sets in MOS transistor networks |
| 791 | -- | 796 | Uwe Hübner, H. Hinsen, M. Hofebauer, Heinrich Theodor Vierhaus. Mixed level test generation for high fault coverage |
| 797 | -- | 0 | . Session H1: Quality control |
| 799 | -- | 806 | E. Brenner, J. Grabner, M. Moosburger, G. Otschko, K. Schlögl, P. Seifter, J. Song, Ch. Steger, R. Weiss. Design and implementation of a distributed real-time expert-system for fault diagnosis in modular manufacturing systems |
| 807 | -- | 813 | István Erényi, Judit Pongrácz. Quality control in textile industry via machine vision |
| 815 | -- | 0 | . Session H2: Evaluation of parallel systems |
| 817 | -- | 824 | Yehuda Wallach, E. Yaprak. Parallel solution of state-estimation on an IBM ring network |
| 825 | -- | 832 | Agustín Fernández, José María Llabería, Juan J. Navarro, Miguel Valero-García. Performance evaluation of transputer systems with linear algebra problems |
| 833 | -- | 0 | . Session H3: Testing methods |
| 835 | -- | 842 | Xinli Gu, Krzysztof Kuchcinski, Zebo Peng. Testability measure with reconvergent fanout analysis and its applications |
| 843 | -- | 850 | András Pataricza. Remarks on the use of Reed-Solomon codes in signature analysis |
| 851 | -- | 0 | . Session H4: VLSI testing and fault modelling II |
| 853 | -- | 859 | M. J. Aguado, J. L. Conesa, E. de la Torre, J. Uceda. A new approach on fault list handling for faster fault elimination and direct test vector generation |
| 861 | -- | 868 | Guy A. S. Wingate, Clive Preece. Analysis of failure data collected from a TMR microprocessor controller |