| 455 | -- | 0 | Massimo Vanzi. Editorial |
| 456 | -- | 461 | David Veyrié, Olivier Gilard, Kevin Sanchez, Sébastien Lhuillier, Frédéric Bourcier. New methodology for the assessment of the thermal resistance of laser diodes and light emitting diodes |
| 462 | -- | 466 | Daniel T. Cassidy, Chadwick K. Hall, Othman Rehioui, Laurent Bechou. Strain estimation in III-V materials by analysis of the degree of polarization of luminescence |
| 467 | -- | 470 | Matteo Meneghini, Nicola Trivellin, Kenji Orita, Masaaki Yuri, Tsuyoshi Tanaka, Daisuke Ueda, Enrico Zanoni, Gaudenzio Meneghesso. Reliability evaluation for Blu-Ray laser diodes |
| 471 | -- | 478 | G. Mura, Massimo Vanzi. The interpretation of the DC characteristics of LED and laser diodes to address their failure analysis |
| 479 | -- | 480 | Tong Yan Tee, Xuejun Fan, Yi-Shao Lai. Advances in Wafer Level Packaging (WLP) |
| 481 | -- | 488 | Cheng-Ta Ko, Kuan-Neng Chen. Wafer-level bonding/stacking technology for 3D integration |
| 489 | -- | 497 | Li-Cheng Shen, Chien-Wei Chien, Hsien-Chie Cheng, Chia-Te Lin. Development of three-dimensional chip stacking technology using a clamped through-silicon via interconnection |
| 498 | -- | 506 | Theresa Sze, Darko Popovic, Jing Shi, Yi-Shao Lai, James G. Mitchell, Bruce Guenin, Tsung-Yueh Tsai, Chin-Li Kao, Matthew Giere. Early experience with in situ chip-to-chip alignment characterization of Proximity Communication flip-chip package |
| 507 | -- | 513 | Changsoo Jang, Byeng Dong Youn, Ping F. Wang, Bongtae Han, Suk-Jin Ham. Forward-stepwise regression analysis for fine leak batch testing of wafer-level hermetic MEMS packages |
| 514 | -- | 521 | Yong Liu. Trends of power semiconductor wafer level packaging |
| 522 | -- | 527 | Jiunn Chen, Yi-Shao Lai, Chueh-An Hsieh, Chia Yi Hu. Redistribution in wafer level chip size packaging technology for high power device applications: Process and design considerations |
| 528 | -- | 535 | Hendrik Pieter Hochstenbach, Willem D. van Driel, D. G. Yang, J. J. M. Zaal, E. Bagerman. Designing for reliability using a new Wafer Level Package structure |
| 536 | -- | 546 | X. J. Fan, B. Varia, Q. Han. Design and optimization of thermo-mechanical reliability in wafer level packaging |
| 547 | -- | 555 | P. Dandu, X. J. Fan, Y. Liu, C. Diao. Finite element modeling on electromigration of solder joints in wafer level packages |
| 556 | -- | 563 | Hao-Yuan Chang, Wen-Fung Pan, Meng-Kai Shih, Yi-Shao Lai. Geometric design for ultra-long needle probe card for digital light processing wafer testing |
| 564 | -- | 576 | Y. A. Su, L. B. Tan, T. Y. Tee, V. B. C. Tan. Rate-dependent properties of Sn-Ag-Cu based lead-free solder joints for WLCSP |