Journal: IEEE Transactions on Computers

Volume 29, Issue 9

763 -- 776David A. Padua, David J. Kuck, Duncan H. Lawrie. High-Speed Multiprocessors and Compilation Techniques
777 -- 791Dhiraj K. Pradhan, Kolar L. Kodandapani. A Uniform Representation of Single- and Multistage Interconnection Networks Used in SIMD Machines
791 -- 801Howard Jay Siegel. The Theory Underlying the Partitioning of Permutation Networks
801 -- 811Chuan-lin Wu, Tse-Yun Feng. The Reverse-Exchange Interconnection Network
811 -- 817Carla Schlatter Ellis. Concurrent Search and Insertion in AVL Trees
818 -- 825Ossama Ibrahim El-Dessouki, Wing H. Huen. Distributed Enumaration on Between Computers
826 -- 831Stephen J. Allan, Arthur E. Oldehoeft. A Flow Analysis Procedure for the Translation of High-Level Languages to a Data Flow Language
831 -- 836Kai Hwang, Lionel M. Ni. Resource Optimization of a Parallel Computer for Multiple Vector Processing
837 -- 840Kenneth E. Batcher. Design of a Massively Parallel Processor
841 -- 844Anthony P. Reeves, John D. Bruner. Efficient Function Implementation for Bit-Serial Parallel

Volume 29, Issue 8

681 -- 688Ikuo Nishioka, Takuji Kurimoto, Seiji Yamamoto, Toru Chiba, Isao Shirakawa, Hiroshi Ozaki. An Approach to Gate Assignment and Module Placement for Printed Wiring Boards
689 -- 694Sheldon S. L. Chang. Multiple-Read Single-Write Memory and Its Applications
694 -- 702Chuan-lin Wu, Tse-Yun Feng. On a Class of Multistage Interconnection Networks
703 -- 709Jan Weglarz. Multiprocessor Scheduling with Memory Allocation - A Deterministic Approach
710 -- 719George P. Engelberg, James A. Howard, Duncan A. Mellichamp. Job Scheduling in a Single-Node Hierarchical Network for Process Control
720 -- 731John F. Meyer. On Evaluating the Performability of Degradable Computing Systems
732 -- 736Masaru Yamamoto. A Method for Minimizing Incompletely Specified Sequential Machines
736 -- 737Janak H. Patel. An Alternative to the Distributed Pipeline
737 -- 738Peter Klein, Mike Paterson. Asymtotically Optimal Circuit for a Storage Access Function
738 -- 740Richard W. Heuft, Warren D. Little. Convolution Computer
740 -- 741C. K. Yuen. Negabinary A/D Conversion
741 -- 746Karl E. Stoffers. Test Sets for Combinational Logic - The Edge-Tracing Approach
746 -- 750Edward W. Page. Minimally Testable Reed-Muller Canonical Forms
750 -- 753Jon C. Muzio. Composite Spectra and the Analysis of Switching Circuits
753 -- 756Norman M. Martin, Stephen P. Hufnagel. Conditional-Sum Early Completion Adder Logic
756 -- 757Yakov I. Fet. Comments on A Design of a Fast Cellular Associative Memory for Ordered Retrieval
757 -- 759Wolfgang Coy. A Remark on the Nonminimality of Certain Multiple Fault Detection Algorithms

Volume 29, Issue 7

553 -- 563Kin-Man Chung, Fabrizio Luccio, C. K. Wong. On the Complexity of Sorting in Magnetic Bubble Memory Systems
563 -- 570Frances L. Van Scoy. The Parallel Recognition of Classes of Graphs
571 -- 577Jon Louis Bentley, Derick Wood. An Optimal Worst Case Algorithm for Reporting Intersections of Rectangles
577 -- 595Hiroshi Hagiwara, Shinji Tomita, Shigeru Oyanagi, Kiyoshi Shibayama. A Dynamically Microprogammable Computer with Low-Level Parallelism
596 -- 603Simon S. Lam. Packet Broadcast Networks - A Performance Analysis of the R-ALOHA Protocol
604 -- 611Tich T. Dao, Marc Davio, Colette Gossart. Complex Number Arithmetic with Odd-Valued Logic
611 -- 618Samuel T. Chanson, Prem S. Sinha. Optimization of Memory Hierarchies in Multiprogrammed Computer Systems With Fixed Cost Constraint
618 -- 631Francis Y. L. Chin, K. Samson Fok. Fast Sorting Algorithms on Uniform Ladders (Multiple Shift-Register Loops)
632 -- 638Omar Wing, John W. Huang. A Computation Model of Parallel Solution of Linear Equations
639 -- 648Bulent I. Dervisoglu, Howard A. Sholl. Theory and Design of Mixed-Mode Sequential Machines
648 -- 656John C. Sutton, Jon G. Bredeson. Minimal Redundant Logic for High Reliability and Irredundant Testability
657 -- 659William A. Porter. Polylogic Realization of Switching Functions
659 -- 662Chris R. Jesshope. Some Results Concerning Data Routing in Array Processors
662 -- 665Moiez A. Tapia, Jerry H. Tucker. Complete Solution of Boolean Equations
665 -- 668Bella Bose, T. R. N. Rao. Separating and Completely Separating Systems and Linear Codes
668 -- 673René David. Testing by Feedback Shift Register
673 -- 678Jacob Savir. Detection of Single Intermittent Faults in Sequential Circuits

Volume 29, Issue 6

419 -- 429Dong S. Suk, Sudhakar M. Reddy. Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories
429 -- 441Satish M. Thatte, Jacob A. Abraham. Test Generation for Microprocessors
442 -- 451Jacob Savir. Syndrome-Testable Design of Combinational Circuits
451 -- 460Miron Abramovici, Melvin A. Breuer. Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis
461 -- 470Sivanarayana Mallela, Gerald M. Masson. Diagnosis Without Repair for Hybrid Fault Situations
471 -- 481Dhiraj K. Pradhan. A New Class of Error-Correcting/Detecting Codes for Fault-Tolerant Computer Applications
482 -- 491Bengt E. Ossfeldt, Ingmar Jonsson. Recovery and Diagnostics in the Central Control of the AXE Switching System
492 -- 500Richard M. Sedmak, Harris L. Liebergot. Fault Tolerance of a General Purpose Computer Implemented by Very Large Scale Integration
501 -- 509John F. Meyer, David G. Furchtgott, Liang T. Wu. Performability Evaluation of the SIFT Computer
510 -- 514James E. Smith. Measures of the Effectiveness of Fault Signature Analysis
514 -- 518René David, Pascale Thévenod-Fosse. Minimal Detecting Transition Sequences: Application to Random Testing
518 -- 522Vinod K. Agarwal. Multiple Fault Detection in Programmable Logic Arrays
523 -- 527Mark G. Karpovsky, Stephen Y. H. Su. Detection and Location of Input and Feedback Bridging Faults Among Input and Output Lines
527 -- 531J. Galiay, Yves Crouzet, M. Vergniault. Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability
532 -- 537Yves Crouzet, Christian Landrault. Design of Self-Checking MOS-LSI Circuits: Application to a Four-Bit Microprocessor
537 -- 540Daniel Etiemble. Multivalued I:::2:::L Circuits for TSC Checkers
540 -- 546Luca Simoncini, F. Saheban, Arthur D. Friedman. Design of Self-Diagnosable Multiprocessor Systems with Concurrent Computation and Diagnosis
546 -- 549P. A. Lee, N. Ghani, K. Heron. A Recovery Cache for the PDP-11

Volume 29, Issue 5

337 -- 340Mark R. Brown, David P. Dobkin. An Improved Lower Bound on Polynomial Multiplication
341 -- 353Earl E. Swartzlander Jr., Barry K. Gilbert. Arithmetic for Ultra-High-Speed Tomography
354 -- 359Yehuda Wallach, Victor Konrad. On Block-Parallel Methods for Solving Linear Equations
360 -- 371Raphael A. Finkel, Marvin H. Solomon. Processor Interconnection Strategies
371 -- 384Chin-Hwa Lee. Queueing Analysis of Global Locking Synchronization Schemes for Multicopy Databases
385 -- 392Hossein Jafari, T. G. Lewis, John D. Spragins. Simulation of a Class of Ring-Structured Networks
393 -- 398Daniel Gajski. Parallel Compressors
398 -- 400William W. Warlick Jr., John E. Hershey. High-Speed ::::M::::-Sequence Generators
400 -- 403K. Wayne Current. Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders
403 -- 405K. Wayne Current. A High Data-Rate Digital Output Correlator Design
405 -- 408Takeomi Tamesada. Sequential Machines Having Quasi-Stable States
408 -- 410Dennis R. Morgan. Autocorrelation Function of Sequential ::::M::::-Bit Words Taken from an ::::N::::-Bit Shift Register (PN) Sequence
410 -- 416Jacob Savir. Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection

Volume 29, Issue 4

269 -- 277Meghanad D. Wagh, H. Ganesh. A New Algorithm for the Discrete Cosine Transform of Arbitrary Number of Points
278 -- 287Anthony P. Reeves. A Systematically Designed Binary Array Processor
288 -- 299Vinod K. Agarwal, Gerald M. Masson. Generic Fault Characterizations for Table Look-Up Coverage Bounding
300 -- 308Jesse H. Jenkins, James A. Howard. Control Overhead - A Performance Metric for Evaluating Control-Unit Designs
308 -- 316John L. Bruno, John W. Jones III, Kimming So. Deterministic Scheduling with Pipelined Processors
317 -- 323Hideo Kitajima. A Symmetric Cosine Transform
324 -- 325Ronald V. Book, Sai Choi Kwan. On Uniquely Decipherable Codes with Two Codewords
325 -- 329R. W. Holgate, Roland N. Ibbett. An Analysis of Instruction-Fetching Strategies in Pipelined Computers
329 -- 331V. E. Vickers, J. Silverman. A Technique for Generating Specialized Gray Codes
331 -- 333David Paul Maher. On Fourier Transforms Over Extensions of Finite Rings
333 -- 0P. S. Kamat. Comments on "Algorithm for Fast Evaluation of Time Functions"

Volume 29, Issue 3

213 -- 222Douglas Stott Parker Jr.. Notes on Shuffel/Exchange-Type Switching Networks
223 -- 235Melvin A. Breuer, Arthur D. Friedman. Functional Level Primitives in Test Generation
235 -- 248Jean Davies Lesser, John J. Shedletsky. An Experimental Delay Test Generator for LSI Logic
249 -- 254John P. Hayes. Testing Memories for Single-Cell Pattern-Sensitive Faults
254 -- 258Stephen Y. H. Su, Edgar DuCasse. A Hardware Redundancy Reconfiguration Scheme for Tolerating Multiple Module Failures
258 -- 261Everett L. Johnson. A Digital Quarter Square Multiplier
261 -- 267Israel Koren, Eitan Sadeh. A New Approach to the Evaluation of the Reliability of Digital Systems

Volume 29, Issue 2

68 -- 79Gene L. Haviland, Al A. Tuszynski. A CORDIC Arithmethic Processor Chip
79 -- 88Michel C. Rahier, Paul G. A. Jespers. Dedicated LSI for a Microprocessor-Controlled Hand-Carried OCR System
89 -- 96Yuzo Kita, Noboru Yamaguchi, Mamoru Sugie, Shigeru Yoshizawa. The Development of a Bubble Memory Controller for Low-Cost File Use
97 -- 102Matt Townsend, Marcian E. Hoff Jr., Robert E. Holm. An NMOS Microprocessor for Analog Signal Processing
102 -- 107Tsuneo Funabashi, Katsuaki Takagi, Toshiro Tsukada, Hideo Nakamura, Michio Hara. An NMOS Microcomputer Peripheral Interface Unit Incorporating an Analog-to-Digital Converter
108 -- 116David A. Patterson, Carlo H. Séquin. Design Considerations for Single-Chip Computers of the Future
116 -- 124Alan J. Weissberger. An LSI Implementation of an Intelligent CRC Computer and Programmable Character Comparator
126 -- 134Rodger A. Cliff. Acceptable Testing of VLSI Components Which Contain Error Correctors
134 -- 144Jan Zeman, H. Troy Nagle Jr.. A High-Speed Microprogrammable Digital Signal Processor Employing Distributed Arithmetic
145 -- 149Ayakannu Mathialagan, Nripendra N. Biswas. Optimal Interconnections in the Design of Microprocessors and Digital Systems
149 -- 160Jega A. Arulpragasam, Robert A. Giggi, Richard F. Lary, Daniel T. Sullivan, Chin-Chang Wu. Modular Minicomputers Using Microprocessors
161 -- 180John J. Lenahan, Fergus K. Fung. Performance of Cooperative Loosely Coupled Microprocessor Architectures in an Interactive Data Base Task
180 -- 190Daniel Tabak, G. Jack Lipovski. MOVE Architecture in Digital Controllers
191 -- 195K. Wayne Current. High Density Integrated Computing Circuitry with Multiple Valued Logic
195 -- 199Robert J. Inkol, Savvas G. Chamberlain. Design and Realization of a Two-Level 64K Byte CCD Memory System for Microcomputer Applications
200 -- 206Rodger A. Cliff. Digital Multiplexing of Analog Data in a Microprocessor Controlled Data Acquisition System
206 -- 208J. F. Burnell, S. C. Crist, Mohammed Arozullah. Microprocessor Utilization in Satellite-Born Packet Switching
208 -- 211M. J. Ellis, G. R. Hovey, T. E. Stapinski. MTEC: A Microprocessor System for Astronomical Telescope and Instrument Control

Volume 29, Issue 12

1038 -- 1052Rami R. Razouk, Gerald Estrin. Modeling and Verification of Communication Protocols in SARA: The X.21 Interface
1052 -- 1060Parviz Kermani, Leonard Kleinrock. A Tradeoff Study of Switching Systems in Computer Communication Networks
1060 -- 1086Michael J. Flynn, John L. Hennessy. Parallelism and Representation Problems in Distributed Systems
1060 -- 1068Georges Gardarin, Wesley W. Chu. A Distributed Control Algorithm for Reliably and Consistently Updating Replicated Databases
1068 -- 1080Peter P. Chen, Jacky Akoka. Optimal Design of Distributed Information Systems
1087 -- 1094Mario J. Gonzalez Jr., Bernard W. Jordan Jr.. A Framework for the Quantitative Evaluation of Distributed Computer Systems
1095 -- 1103James R. McGraw. Data Flow Computing - Software Development
1104 -- 1113Reid G. Smith. The Contract Net Protocol: High-Level Communication and Control in a Distributed Problem Solver
1114 -- 1132Steven I. Kartashev, Svetlana P. Kartashev. Problems of Designing Supersystems with Dynamic Architectures
1133 -- 1144Larry D. Wittie, André M. Van Tilborg. MICROS, A Distributed Operating System for MICRONET, A Reconfigurable Network Computer
1144 -- 1163Victor R. Lesser, Lee D. Erman. Distributed Interpretation: A Model and Experiment

Volume 29, Issue 11

957 -- 970Keith L. Doty, Joel D. Greenblatt, Stanley Y. W. Su. Magnetic Bubble Memory Architectures for Supporting Associative Searching of Relational Databases
971 -- 977Wesley W. Chu, Michael Yih-Chung Shen. Hierarchical Routing and Flow Control Policy (HRFC) for Packet Switched Networks
978 -- 985Ayee Goundan, John P. Hayes. Identification of Equivalent Faults in Logic Networks
986 -- 994Abraham Kandel, Joan M. Francioni. On the Properties and Applications of Fuzzy-Valued Switching Functions
994 -- 1001N. K. Samari, G. Michael Schneider. A Queueing Theory-Based Analytic Model of a Distributed Computer Network
1002 -- 1011Ying W. Ng, Algirdas Avizienis. A Unified Reliability Model for Ault-Tolerant Computers
1013 -- 1016Stephen C. Crist. Synthesis of Combinational Logic Using Decomposition and Probability
1017 -- 1020J. M. Glass. An Efficient Method for Improving Reliability of a Pipeline FFT
1020 -- 1025Kewal K. Saluja. Synchronous Sequential Machines: A Modular and Testable Design
1025 -- 1029Sumit Dasgupta, Carlos R. P. Hartmann, Luther D. Rudolph. Dual-Mode Logic for Function-Independent Fault Testing
1029 -- 1032K. M. Chung, C. K. Wong. Construction of a Generalized Connector with 5.8 ::::n:::: log::2:: ::::n:::: Edges
1032 -- 1035Dharma P. Agrawal. On Negabinary-Binary Arithmetic Relationships an Their Hardware Reciprocity

Volume 29, Issue 10

845 -- 854King-sun Fu. Recent Developments in Pattern Recognition
855 -- 863Gian Carlo Bongiovanni, Fabrizio Luccio. Maintaining Sorted Files in a Magnetic Bubble Memory
864 -- 874Kin-Man Chung, Fabrizio Luccio, C. K. Wong. A Tree Storage Scheme for Magnetic Bubble Memories
874 -- 883Robert B. Tilove. Set Membership Classification: A Unified Approach to Geometric Intersection Problems
884 -- 889Pierre G. Jansen, Joep L. W. Kessels. The DIMOND: A Component for the Modular Construction of Switching Networks
889 -- 898Anthony S. Wojcik, Kwang-Ya Fang. On the Design of Three-Valued Asynchronous Modules
899 -- 905Graham A. Jullien. Implementation of Multiplication, Modulo ::::a:::: Prime Number, with Applications to Number Theoretic Transforms
905 -- 919Kim P. Gostelow, Robert E. Thomas. Performance of a Simulated Dataflow Computer
920 -- 927Steven E. Elkind, Daniel P. Siewiorek. Reliability and Performance of Error-Correcting Memory and Register Arrays
927 -- 928Grazia Lotti, Francesco Romani. Application of Approximating Algorithms to Boolean Matrix Multiplication
929 -- 931H. T. Mouftah, K. C. Smith, Zvonko G. Vranesic. Ternary Rate-Multipliers
931 -- 934Marc Davio. Read-Only Memory Implementation of Discrete Function
934 -- 937Udi Manber. System Diagnosis with Repair
937 -- 941James R. Armstrong. The Complexity of Computational Circuits Versus Radix
942 -- 946Luigi Dadda. Composite Parallel Counters
946 -- 950Earl E. Swartzlander Jr.. Merged Arithmetic
950 -- 953Sandy Leinwand, T. Lamdan. Dynamic Boolean Algebras
953 -- 0John W. Stoughton. Modification of A Least Mean Squares CUBIC Algorithm for On-Line Differential of Sampled Analog Signals

Volume 29, Issue 1

2 -- 20Tomlinson Gene Rauscher, Phillip M. Adams. Microprogramming: A Tutorial and Survey of Recent Developments
20 -- 27Chris R. Jesshope. The Implementation of Fast Radix 2 Transforms on Array Processors
28 -- 32Hanan Samet. Efficient On-Line Proofs of Equalities and Inequalities of Formulas
33 -- 44Ayee Goundan, John P. Hayes. Design of Totally Fault Locatable Combinational Networks
44 -- 49Shashi K. Mehra, J. W. Wong, Jayanti C. Majithia. A Comparative Study of Some Two-Processor Organizations
50 -- 54Paul Cull. Tours of Graphs, Digraphs, and Sequential Machines
55 -- 59Kolar L. Kodandapani, Dhiraj K. Pradhan. Undetectability of Bridging Faults and Validity of Stuck-At Fault Test Sets
59 -- 61R. M. M. Oberman. Comments on Modular Replacement of Combinational Switching Networks