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| 1904 | -- | 1921 | Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Christos P. Sotiriou. Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications |
| 1922 | -- | 1934 | Prasenjit Basu, Sayantan Das, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix, Roy Armoni. Design-Intent Coverage - A New Paradigm for Formal Property Verification |
| 1935 | -- | 1949 | J.-G. Lee, C. M. Kyung. PrePack: Predictive Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation |
| 1950 | -- | 1968 | Sebastien Bilavarn, Guy Gogniat, Jean Luc Philippe, Lilian Bossuet. Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations |
| 1969 | -- | 1989 | Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. Use of Computation-Unit Integrated Memories in High-Level Synthesis |
| 1990 | -- | 2000 | Dong-U Lee, Altaf Abdul Gaffar, Ray C. C. Cheung, Oskar Mencer, Wayne Luk, George A. Constantinides. Accuracy-Guaranteed Bit-Width Optimization |
| 2001 | -- | 2011 | Sarma B. K. Vrudhula, Janet Meiling Wang, Praveen Ghanta. Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations |
| 2012 | -- | 2022 | Anup Hosangadi, Farzan Fallah, Ryan Kastner. Optimizing Polynomial Expressions by Algebraic Factorization and Common Subexpression Elimination |
| 2023 | -- | 2034 | Yan Lin, Lei He. Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction |
| 2035 | -- | 2051 | Manish Verma, Lars Wehmeyer, Peter Marwedel. Cache-Aware Scratchpad-Allocation Algorithms for Energy-Constrained Embedded Systems |
| 2052 | -- | 2061 | Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy. Modeling and Analysis of Leakage Currents in Double-Gate Technologies |
| 2062 | -- | 2075 | N. Wong, V. Balakrishnan, C.-K. Koh, T. S. Ng. Two Algorithms for Fast and Accurate Passivity-Preserving Model Order Reduction |
| 2076 | -- | 2087 | Andrew A. Kennings, Kristofer Vorwerk. Force-Directed Methods for Generic Placement |
| 2088 | -- | 2102 | Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Elaheh Bozorgzadeh. Statistical Analysis and Design of HARP FPGAs |
| 2103 | -- | 2117 | Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. RTL-Aware Cycle-Accurate Functional Power Estimation |
| 2118 | -- | 2128 | J. Cervenka, W. Wessner, E. Al-Ani, Tibor Grasser, Siegfried Selberherr. Generation of Unstructured Meshes for Process and Device Simulation by Means of Partial Differential Equations |
| 2129 | -- | 2139 | W. Wessner, J. Cervenka, Clemens Heitzinger, Andreas Hössinger, Siegfried Selberherr. Anisotropic Mesh Refinement for the Simulation of Three-Dimensional Semiconductor Manufacturing Processes |
| 2140 | -- | 2155 | Ming Zhang, Naresh R. Shanbhag. Soft-Error-Rate-Analysis (SERA) Methodology |
| 2156 | -- | 2169 | Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm. Voltage-Aware Static Timing Analysis |
| 2170 | -- | 2180 | Chandramouli Visweswariah, K. Ravindran, K. Kalafala, Steven G. Walker, S. Narayan, Daniel K. Beece, J. Piaget, N. Venkateswaran, Jeffrey G. Hemmett. First-Order Incremental Block-Based Statistical Timing Analysis |
| 2181 | -- | 2192 | Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker. Simulating Resistive-Bridging and Stuck-At Faults |
| 2193 | -- | 2206 | Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar. Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques |
| 2207 | -- | 2218 | Irith Pomeranz, Sudhakar M. Reddy. Generation of Functional Broadside Tests for Transition Faults |
| 2219 | -- | 2227 | Irith Pomeranz, Sudhakar M. Reddy. Using Dummy Bridging Faults to Define Reduced Sets of Target Faults |
| 2228 | -- | 2231 | Marc-André Cantin, Yvon Savaria, D. Prodanos, Pierre Lavoie. A Metric for Automatic Word-Length Determination of Hardware Datapaths |
| 2231 | -- | 2241 | M. Capobianchi, V. Labay, F. Shi, G. Mizushima. Simulating the Electrical Behavior of Integrated Circuit Devices in the Presence of Thermal Interactions |
| 2241 | -- | 2248 | Valentina Ciriani, Anna Bernasconi, Rolf Drechsler. Testability of SPP Three-Level Logic Networks in Static Fault Models |
| 2248 | -- | 2257 | Jacob R. Minz, Sung Kyu Lim. Block-level 3-D Global Routing With an Application to 3-D Packaging |
| 2258 | -- | 2264 | S.-W. Tu, Y.-W. Chang, J.-Y. Jou. RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction |
| 2264 | -- | 2275 | Janet Meiling Wang, Jun Li, Satish K. Yanamanamanda, Lakshmi Kalpana Vakati, Kishore Kumar Muchherla. Modeling the Driver Load in the Presence of Process Variations |
| 2275 | -- | 2282 | Qingwei Wu, Michael S. Hsiao. State Variable Extraction and Partitioning to Reduce Problem Complexity for ATPG and Design Validation |
| 2282 | -- | 2286 | Shu Yan, Vivek Sarin, Weiping Shi. Fast 3-D Capacitance Extraction by Inexact Factorization and Reduction |
| 2287 | -- | 2293 | Bo Yang, Kaijie Wu, Ramesh Karri. Secure Scan: A Design-for-Test Architecture for Crypto Chips |