| 613 | -- | 617 | Ze-kun Zhou, Yue Shi, Chao Gou, Xia Wang, Gang Wu, Jie-fei Feng, Zhuo Wang, Bo Zhang. A Resistorless Low-Power Voltage Reference |
| 618 | -- | 622 | Joonhoi Hur, Hyoungsoo Kim, Ockgoo Lee, Kwan-Woo Kim, Franklin Bien, Kyutae Lim, Chang-Ho Lee, Joy Laskar. A Multilevel Class-D CMOS Power Amplifier for an Out-Phasing Transmitter With a Nonisolated Power Combiner |
| 623 | -- | 627 | Peng Wang, Trond Ytterdal. A 54-µW Inverter-Based Low-Noise Single-Ended to Differential VGA for Second Harmonic Ultrasound Probes in 65-nm CMOS |
| 628 | -- | 632 | Bibhu Datta Sahoo, Amol Inamdar. Thermal-Noise-Canceling Switched-Capacitor Circuit |
| 633 | -- | 637 | Chih-Lu Wei, Shen-Iuan Liu. A Digital PLL Using Oversampling Delta-Sigma TDC |
| 638 | -- | 642 | Yongkui Yang, Jun Zhou, Xin Liu, Jia Hao Cheong, Wang Ling Goh. A 151-nW Adaptive Delta-Sampling ADC for Ultra-Low Power Sensing Applications |
| 643 | -- | 647 | Liang Wen, Xu Cheng, Keji Zhou, Shudong Tian, Xiaoyang Zeng. Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier |
| 648 | -- | 652 | Georges Kaddoum, Ebrahim Soujeri. NR-DCSK: A Noise Reduction Differential Chaos Shift Keying System |
| 653 | -- | 657 | Marco De Piante, Andrea M. Tonello. On Impedance Matching in a Power-Line-Communication System |
| 658 | -- | 662 | Apsara Ravish Suvarna, Venumadhav Bhagavatula, Jacques C. Rudell. Transformer-Based Tunable Matching Network Design Techniques in 40-nm CMOS |
| 663 | -- | 667 | Tao Yang, Ziyang Meng, Dimos V. Dimarogonas, Karl Henrik Johansson. Periodic Behaviors for Discrete-Time Second-Order Multiagent Systems With Input Saturation Constraints |
| 668 | -- | 672 | Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei. A Fast and Power-Efficient Memory-Centric Architecture for Affine Computation |
| 673 | -- | 677 | Byeong Yong Kong, Hoyoung Yoo, In-Cheol Park. Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes |
| 678 | -- | 682 | Ramtin Zand, Arman Roohi, Soheil Salehi, Ronald F. DeMara. Scalable Adaptive Spintronic Reconfigurable Logic Using Area-Matched MTJ Design |
| 683 | -- | 687 | Mo Huang, Yan Lu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins. A Fully Integrated Digital LDO With Coarse-Fine-Tuning and Burst-Mode Operation |
| 688 | -- | 692 | Dawei Liu, Simon J. Hollis, Harry C. P. Dymond, Neville McNeill, Bernard H. Stark. Design of 370-ps Delay Floating-Voltage Level Shifters With 30-V/ns Power Supply Slew Tolerance |
| 693 | -- | 697 | Wen Sun, Jinhu Lu, Xinghuo Yu, Yao Chen, Shihua Chen. Cooperation of Multiagent Systems With Mismatch Parameters: A Viewpoint of Power Systems |
| 698 | -- | 702 | Michele Bonnin, Fabio L. Traversa, Fabrizio Bonani. Influence of Amplitude Fluctuations on the Noise-Induced Frequency Shift of Noisy Oscillators |
| 703 | -- | 707 | Aimin Jiang, Hon Keung Kwan, Yanping Zhu, Ning Xu, Xiaofeng Liu. Efficient WLS Design of IIR Digital Filters Using Partial Second-Order Factorization |
| 708 | -- | 712 | Mohammad Sadegh Alizadeh, Javad Bagherzadeh, Mohammad Sharifkhani. A Low-Latency QRD-RLS Architecture for High-Throughput Adaptive Applications |