| 2 | -- | 19 | Mani B. Srivastava, Miodrag Potkonjak. Optimum and heuristic transformation techniques for simultaneous optimization of latency and throughput |
| 20 | -- | 35 | Mani B. Srivastava, Robert W. Brodersen. System level hardware module generation |
| 36 | -- | 48 | Debabrata Ghosh, S. K. Nandy. Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology |
| 49 | -- | 58 | Mircea R. Stan, Wayne P. Burleson. Bus-invert coding for low-power I/O |
| 59 | -- | 71 | Michael Nicolaidis, Vladimir Castro Alves, Hakim Bederr. Testing complex couplings in multiport memories |
| 72 | -- | 83 | Krishnendu Chakrabarty, John P. Hayes. Cumulative balance testing of logic circuits |
| 84 | -- | 98 | Jun Dong Cho, M. Sarrafzadeh. A buffer distribution algorithm for high-performance clock net optimization |
| 99 | -- | 111 | Brian S. Cherkauer, Eby G. Friedman. A unified design methodology for CMOS tapered buffers |
| 112 | -- | 123 | Steven G. Duvall. A practical methodology for the statistical design of complex logic products for performance |
| 124 | -- | 135 | Jiao Fan, D. Zaleta, Chung-Kuan Cheng, S.-H. Lee. Physical models and algorithms for optoelectronic MCM layout |
| 136 | -- | 141 | M. Agarwala, Poras T. Balsara. An architecture for a DSP field-programmable gate array |
| 141 | -- | 146 | Nan-Chi Chou, Chung-Kuan Cheng. On general zero-skew clock net construction |
| 146 | -- | 152 | Shyue-Kung Lu, Jen-Chuan Wang, Cheng-Wen Wu. C-testable design techniques for iterative logic arrays |