| 157 | -- | 172 | Florin Balasa, Francky Catthoor, Hugo De Man. Background memory area estimation for multidimensional signal processing systems |
| 173 | -- | 187 | Paul E. Landman, Jan M. Rabaey. Architectural power analysis: The dual bit type method |
| 188 | -- | 200 | Ashok K. Chandra, Vijay S. Iyengar, D. Jameson, R. V. Jawalekar, Indira Nair, Barry K. Rosen, Michael P. Mullen, J. Yoon, R. Armoni, Daniel Geist, Yaron Wolfsthal. AVPGEN-A test generator for architecture verification |
| 201 | -- | 214 | R. Vemuri, R. Kalyanaraman. Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming |
| 215 | -- | 230 | Andrés Takach, Wayne Wolf. Scheduling constraint generation for communicating processes |
| 231 | -- | 244 | Brian A. A. Antao, Arthur J. Brodersen. ARCHGEN: Automated synthesis of analog systems |
| 245 | -- | 253 | Dan Picker, Ronald D. Fellman. A VLSI priority packet queue with inheritance and overwrite |
| 254 | -- | 263 | Hussein M. Alnuweiri, Sadiq M. Sait. Efficient network folding techniques for routing permutations in VLSI |
| 264 | -- | 272 | P. Day, J. V. Woods. Investigation into micropipeline latch design styles |
| 273 | -- | 291 | Timothy M. Burks, Karem A. Sakallah, Trevor N. Mudge. Critical paths in circuits with level-sensitive latches |
| 292 | -- | 301 | Vojin G. Oklobdzija, David Villeger. Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology |
| 302 | -- | 310 | Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu. A practical current sensing technique for I::DDQ:: testing |
| 311 | -- | 322 | Qingjian Yu, Ernest S. Kuh. Exact moment matching model of transmission lines and application to interconnect delay estimation |
| 323 | -- | 327 | Hyunchul Shin, Chunghee Kim. Performance-oriented technology mapping for LUT-based FPGA s |
| 327 | -- | 333 | Uming Ko, T. Balsara, Wai Lee. Low-power design techniques for high-performance CMOS adders |
| 333 | -- | 338 | Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel. Sequential circuit testability enhancement using a nonscan approach |
| 338 | -- | 341 | Shih-Lien Lu. Implementation of micropipelines in enable/disable CMOS differential logic |