| 17 | -- | 31 | Herbert Dawid, Gerhard Fettweis, Heinrich Meyr. A CMOS IC for Gb/s Viterbi decoding: system design and VLSI implementation |
| 32 | -- | 41 | Jeffrey C. Gealow, F. P. Herrmann, L. T. Hsu, Charles Sodini. System design for pixel-parallel image processing |
| 42 | -- | 55 | Mani B. Srivastava, Anantha P. Chandrakasan, Robert W. Brodersen. Predictive system shutdown and other architectural techniques for energy efficient programmable computation |
| 56 | -- | 69 | Jean Vuillemin, Patrice Bertin, Didier Roncin, Mark Shand, H. H. Touati, Philippe Boucard. Programmable active memories: reconfigurable systems come of age |
| 70 | -- | 82 | Daniel D. Gajski, Sanjiv Narayan, Loganath Ramachandran, Frank Vahid, Peter Fung. System design methodologies: aiming at the 100 h design cycle |
| 83 | -- | 97 | Pao-Ann Hsiung, Sao-Jie Chen, Tsung-Chien Hu, Shih-Chiang Wang. PSM: an object-oriented synthesis approach to multiprocessor system design |
| 98 | -- | 112 | Ti-Yen Yen, Wayne Wolf. An efficient graph algorithm for FSM scheduling |
| 113 | -- | 129 | Michael A. Riepe, João P. Marques Silva, Karem A. Sakallah, Richard B. Brown. Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation |
| 130 | -- | 133 | Michele Favalli, Cecilia Metra. Sensing circuit for on-line detection of delay faults |
| 134 | -- | 137 | Sebastian T. J. Fenn, Mohammed Benaissa, David Taylor. Finite field inversion over the dual basis |
| 137 | -- | 140 | D. J. Kinniment. An evaluation of asynchronous addition |
| 141 | -- | 145 | Chin-Long Wey. Built-in self-test (BIST) design of high-speed carry-free dividers |
| 146 | -- | 0 | V. Chandramouli, Erik Brunvand, Kent F. Smith. Self-Timed Design in GaAs - Case Study of a High-Speed, Parallel Multiplier |