| 5 | -- | 6 | Magdy A. Bayoumi. Introduction |
| 9 | -- | 19 | Catherine H. Gebotys. An optimal methodology for synthesis of DSP multichip architectures |
| 21 | -- | 34 | Sati Banerjee, Paul M. Chau, Ronald D. Fellman. Rapid prototyping methodology for multiprocessor implementation of digital signal processing systems |
| 35 | -- | 50 | Hyeong-Kyo Kim, Thomas P. Barnwell. A design synthesis system for recursive DSP algorithms represented by fully specified flow graphs |
| 51 | -- | 74 | Mirjam Schönfeld, Jens Franzen, Markus Schwiegershausen, Peter Pirsch, Uwe Vehlies, Andreas Münzner. The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques |
| 75 | -- | 96 | Ching-Yi Wang, Keshab K. Parhi. Resource-constrained loop list scheduler for DSP algorithms |
| 97 | -- | 112 | Marc Pauwels, Gert Goossens, Francky Catthoor, Hugo De Man. Formalisation of multi-precision arithmetic for high-level synthesis of DSP architectures |
| 113 | -- | 131 | Yoav Yaacoby, Peter R. Cappello. Converting affine recurrence equations to quasi-uniform recurrence equations |
| 133 | -- | 150 | Yin-Tsung Hwang, Yu Hen Hu. A unified partitioning and scheduling scheme for mapping multi-stage regular iterative algorithms onto processor arrays |
| 151 | -- | 168 | Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri, Dhamin Al-Khalili. Design techniques for fault-tolerant systolic arrays |
| 169 | -- | 187 | Nam Ling. A special purpose formal verifier for systolic designs in DSP applications |