The following publications are possibly variants of this publication:
- Test Time Reduction in EDT Bandwidth Management for SoC DesignsJakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer. tcad, 32(11):1776-1786, 2013. [doi]
- Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs"Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer. tcad, 33(1):167, 2014. [doi]
- EDT bandwidth management - Practical scenarios for large SoC designsJakub Janicki, Jerzy Tyszer, W.-T. Cheng, Y. Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Y. Dong, G. Giles. itc 2013: 1-10 [doi]
- EDT channel bandwidth management in SoC designs with pattern-independent test access mechanismJakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski. itc 2011: 1-9 [doi]
- Dynamic channel allocation for higher EDT compression in SoC designsMark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer. itc 2010: 265-274 [doi]
- Test Compression Improvement with EDT Channel Sharing in SoC DesignsYu Huang, Mark Kassab, Jay Jahangiri, Janusz Rajski, Wu-Tung Cheng, Dongkwan Han, Jihye Kim, Kun Young Chung. natw 2014: 22-31 [doi]
- Bandwidth-aware test compression logic for SoC designsJakub Janicki, Jerzy Tyszer, Grzegorz Mrugalski, Janusz Rajski. ets 2012: 1-6 [doi]