ESD Protection for Mixed-Voltage I/O in LowVoltage Thin-Oxide CMOS - researchr publication related

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Ming-Dou Ker, Wei-Jen Chang, Chang-Tzu Wang, Wen-Yi Chen. ESD Protection for Mixed-Voltage I/O in LowVoltage Thin-Oxide CMOS. In 2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006. pages 2230-2237, IEEE, 2006. [doi]

The following publications are possibly variants of this publication:

Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technologyMing-Dou Ker, Wei-Jen Chang. mr, 47(1):27-35, 2007. [doi]

Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOSMing-Dou Ker, Chang-Tzu Wang. cicc 2009: 689-696 [doi]

ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS ProcessMing-Dou Ker, Chien-Hui Chuang, Kuo-Chun Hsu, Wen-Yu Lo. isqed 2002: 331-336 [doi]

Overview and Design of Mixed-Voltage I/O Buffers With Low-Voltage Thin-Oxide CMOS TransistorsMing-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai. tcas, 53(9):1934-1945, 2006. [doi]

Electrostatic discharge protection design for mixed-voltage CMOS I/O buffersMing-Dou Ker, Chien-Hui Chuang. jssc, 37(8):1046-1055, 2002. [doi]

ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuitMing-Dou Ker, Hsin-Chyh Hsu. tcas, 52-I(1):44-53, 2005. [doi]

0.9 V to 5 V Bidirectional Mixed-Voltage I/O Buffer With an ESD Protection Output StageChua-Chin Wang, Ron-Chi Kuo, Jen-Wei Liu. tcas, 57-II(8):612-616, 2010. [doi]

Design of 2.5 V/5 V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuitMing-Dou Ker, Chia-Sheng Tsai. iscas 2003: 97-100 [doi]

Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal LevelsMing-Dou Ker, Wei-Jen Chang, Wen-Yu Lo. isqed 2004: 433-438 [doi]

ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structureKun-Hsien Lin, Ming-Dou Ker. iscas 2005: 1182-1185 [doi]

Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS processYuan-Wen Hsiao, Ming-Dou Ker. mr, 49(6):650-659, 2009. [doi]

ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS processYuan-Wen Hsiao, Ming-Dou Ker, Po-Yen Chiu, Chun Huang, Yuh-Kuang Tseng. socc 2007: 277-280 [doi]

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