The following publications are possibly variants of this publication:
- A design-for-test solution for monolithic 3D integrated circuitsRan Wang, Krishnendu Chakrabarty. ets 2016: 1-6 [doi]
- Test and Design-for-Testability Solutions for Monolithic 3D Integrated CircuitsAbhishek Koneru, Krishnendu Chakrabarty. glvlsi 2019: 457-462 [doi]
- Testing and design-for-testability solutions for 3D integrated circuitsKrishnendu Chakrabarty. ddecs 2011: 5 [doi]
- Test and Design-for-Testability Solutions for 3D Integrated CircuitsKrishnendu Chakrabarty, Mukesh Agrawal, Sergej Deutsch, Brandon Noia, Ran Wang, Fangming Ye. ipsj, 7:56-73, 2014. [doi]
- A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated CircuitsAbhishek Koneru, Sukeshwar Kannan, Krishnendu Chakrabarty. tcad, 38(10):1942-1955, 2019. [doi]
- Design Automation and Test Solutions for Monolithic 3D ICsLingjun Zhu, Arjun Chaudhuri, Sanmitra Banerjee, Gauthaman Murali, Pruek Vanna-Iampikul, Krishnendu Chakrabarty, Sung Kyu Lim. jetc, 18(1), 2022. [doi]
- Impact of Electrostatic Coupling and Wafer-Bonding Defects on Delay Testing of Monolithic 3D Integrated CircuitsAbhishek Koneru, Sukeshwar Kannan, Krishnendu Chakrabarty. jetc, 13(4), 2017. [doi]
- Analysis of electrostatic coupling in monolithic 3D integrated circuits and its impact on delay testingAbhishek Koneru, Krishnendu Chakrabarty. ets 2016: 1-6 [doi]