The following publications are possibly variants of this publication:
- A DFT Selection Method for Reducing Test Application Time of System-on-ChipsMasahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara. ieicet, 87-D(3):609-619, 2004. [doi]
- A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the Number of Test Patterns Using Partial MaxSATRyuki Asami, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai. dft 2020: 1-6 [doi]
- A Block Partitioning Method for Region Exhaustive Test to Reduce the Number of Test Patterns and Improve Gate Exhaustive Fault CoverageMomona Mizota, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai. dft 2023: 1-6 [doi]