The following publications are possibly variants of this publication:
- Power Analysis of Bipartition and Dual-Encoding Architecture for Pipelined CircuitsShanq-Jang Ruan, Edwin Naroska, Chia-Lin Ho, Feipei Lai. iccd 2002: 327 [doi]
- A bipartition-codec architecture to reduce power in pipelined circuitsShanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Shyh-Jong Chen, Xian-Jun Huang. iccad 1999: 84-90 [doi]
- ENPCO: an entropy-based partition-codec algorithm to reduce power for bipartition-codec architecture in pipelined circuitsShanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Feipei Lai, Uwe Schwiegelshohn. tvlsi, 10(6):942-949, 2002. [doi]