The following publications are possibly variants of this publication:
- Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAsYuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera. fpga 2008: 257 [doi]
- A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay VariationsKazutoshi Kobayashi, Kazuya Katsuki, Manabu Kotani, Yuuri Sugihara, Yohei Kume, Hidetoshi Onodera. ieicet, 90-C(10):1919-1926, 2007. [doi]
- A yield and speed enhancement scheme under within-die variations on 90nm LUT arrayKazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera. cicc 2005: 601-604 [doi]
- Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devicesKazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera. aspdac 2006: 110-111 [doi]
- A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay VariationsKazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera. ieicet, 90-C(4):699-707, 2007. [doi]
- A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer RegimeKazutoshi Kobayashi, Manabu Kotani, Kazuya Katsuki, Y. Takatsukasa, K. Ogata, Yuuri Sugihara, Hidetoshi Onodera. fpl 2006: 1-4 [doi]