The following publications are possibly variants of this publication:
- Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD ProtectionChih-Ting Yeh, Ming-Dou Ker. jssc, 45(11):2476-2486, 2010. [doi]
- Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on eventsChih-Ting Yeh, Yung-Chih Liang, Ming-Dou Ker. iscas 2011: 1403-1406 [doi]
- The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICsMing-Dou Ker, Kun-Hsien Lin. jssc, 40(8):1751-1759, 2005. [doi]
- Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS processChih-Ting Yeh, Ming-Dou Ker. vlsi-dat 2013: 1-4 [doi]
- On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS ProcessMing-Dou Ker, Po-Yen Chiu, Fu-Yi Tsai, Yeong-Jar Chang. iscas 2009: 2281-2284 [doi]
- Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-µm CMOS technologyShih-Hung Chen, Ming-Dou Ker. mr, 50(6):821-830, 2010. [doi]
- Optimization on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-μm CMOS technologyShih-Hung Chen, Ming-Dou Ker. icecsys 2008: 666-669 [doi]
- Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technologyMing-Dou Ker, Wei-Jen Chang. mr, 47(1):27-35, 2007. [doi]
- Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS ProcessMing-Dou Ker, Wen-Yi Chen, Kuo-Chun Hsu. tcas, 53(10):2187-2193, 2006. [doi]