Abstract is missing.
- PCAM: A Ternary CAM Optimized for Longest Prefix Matching TasksMohammad J. Akhbarizadeh, Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara. 6-11 [doi]
- Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip BusesSrinivasa R. Sridhara, Arshad Ahmed, Naresh R. Shanbhag. 12-17 [doi]
- An Area- and Energy-Efficient Asynchronous Booth Multiplier for Mobile DevicesJustin Hensley, Anselmo Lastra, Montek Singh. 18-25 [doi]
- A High-Frequency Decimal MultiplierRobert D. Kenney, Michael J. Schulte, Mark A. Erle. 26-29 [doi]
- An Efficient Twin-Precision MultiplierMagnus Själander, Henrik Eriksson, Per Larsson-Edefors. 30-33 [doi]
- Defining Wakeup Width for Efficient Dynamic SchedulingAneesh Aggarwal, Manoj Franklin, Oguz Ergin. 36-41 [doi]
- Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache StructureJung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim. 42-47 [doi]
- Thermal-Aware Clustered MicroarchitecturesPedro Chaparro, José González, Antonio González. 48-53 [doi]
- Reducing Issue Queue Power for Multimedia Applications using a Feedback Control AlgorithmYu Bai, R. Iris Bahar. 54-57 [doi]
- A Novel Low-Power Scan Design Technique Using Supply GatingSwarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy. 60-65 [doi]
- Asynchronous Scan-Latch controller for Low Area Overhead DFTMasayuki Tsukisaka, Masashi Imai, Takashi Nanya. 66-71 [doi]
- End-to-End Testability Analysis and DfT Insertion for Mixed-Signal PathsSule Ozev, Alex Orailoglu. 72-77 [doi]
- Functional Illinois Scan Design at RTLHo Fai Ko, Nicola Nicolici. 78-81 [doi]
- On Undetectable Faults in Partial Scan Circuits Using Transparent-ScanIrith Pomeranz, Sudhakar M. Reddy. 82-84 [doi]
- A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI CircuitsHasan Arslan, Shantanu Dutt. 86-92 [doi]
- Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global RoutingTianpei Zhang, Sachin S. Sapatnekar. 93-98 [doi]
- A Two-Layer Bus Routing Algorithm for High-Speed BoardsMuhammet Mustafa Ozdal, Martin D. F. Wong. 99-105 [doi]
- Reticle Floorplanning with Guaranteed Yield for Multi-Project WafersMartin D. F. Wong. 106-110 [doi]
- Fine-Grain Abstraction and Sequential Don t Cares for Large Scale Model CheckingChao Wang, Gary D. Hachtel, Fabio Somenzi. 112-118 [doi]
- Comparative Study of Strategies for Formal Verification of High-Level ProcessorsMiroslav N. Velev. 119-124 [doi]
- A Highly-Efficient Technique for Reducing Soft Errors in Static CMOS CircuitsSrivathsan Krishnamohan, Nihar R. Mahapatra. 126-131 [doi]
- A Signal Integrity Test Bed for PCB BusesJihong Ren, Mark R. Greenstreet. 132-137 [doi]
- A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip RepeatersSaumil Shah, Kanak Agarwal, Dennis Sylvester. 138-143 [doi]
- A General Post-Processing Approach to Leakage Current Reduction in SRAM-Based FPGAsJohn Lach, Jason Brandon, Kevin Skadron. 144-150 [doi]
- Design Methodologies and Architecture Solutions for High-Performance InterconnectsDavide Pandini, Cristiano Forzan, Livio Baldi. 152-159 [doi]
- On-Chip Transparent Wire PipeliningMario R. Casu, Luca Macchiarulo. 160-167 [doi]
- Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated SystemsRadu Marculescu, Diana Marculescu, Larry T. Pileggi. 168-173 [doi]
- Network-on-Chip: The Intelligence is in The WireGérard Mas, Philippe Martin. 174-177 [doi]
- Low Power Test Data Compression Based on LFSR ReseedingJinKyu Lee, Nur A. Touba. 180-185 [doi]
- An Infrastructure IP for On-Chip Clock Jitter MeasurementJui-Jer Huang, Jiun-Lang Huang. 186-191 [doi]
- Diagnosis of Hold Time DefectsZhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski. 192-199 [doi]
- Extending the Applicability of Parallel-Serial Scan DesignsBaris Arslan, Ozgur Sinanoglu, Alex Orailoglu. 200-203 [doi]
- Quality Improvement Methods for System-Level Stimuli GenerationRoy Emek, Itai Jaeger, Yoav Katz, Yehuda Naveh. 204-206 [doi]
- XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level DesignsYinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwini Verma. 208-215 [doi]
- A Flexible Data Structure for Efficient Buffer InsertionRuiming Chen, Hai Zhou. 216-221 [doi]
- Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D SystemsMadhubanti Mukherjee, Ranga Vemuri. 222-227 [doi]
- Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} CircuitsAnup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar. 228-233 [doi]
- Best of Both Latency and ThroughputEd Grochowski, Ronny Ronen, John Paul Shen, Hong Wang 0003. 236-243 [doi]
- Fetch Halting on Critical Load MissesNikil Mehta, Brian Singer, R. Iris Bahar, Michael Leuchtenburg, Richard S. Weiss. 244-249 [doi]
- Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2Grigorios Magklis, José González, Antonio González. 250-255 [doi]
- Gate Sizing and V{t} Assignment for Active-Mode Leakage Power ReductionFeng Gao, John P. Hayes. 258-264 [doi]
- Potential Slack Budgeting with Clock Skew OptimizationKai Wang, Malgorzata Marek-Sadowska. 265-271 [doi]
- A New Statistical Optimization Algorithm for Gate SizingMurari Mani, Michael Orshansky. 272-277 [doi]
- An Architecture for Fast Processing of Large Unstructured Data SetsMark A. Franklin, Roger D. Chamberlain, Michael Henrichs, Berkley Shands, Jason White. 280-287 [doi]
- In-System FPGA Prototyping of an Itanium MicroarchitectureRoland E. Wunderlich, James C. Hoe. 288-294 [doi]
- Adaptive Selection of an Index in a Texture CacheChun-Ho Kim, Lee-Sup Kim. 295-300 [doi]
- Using Circuits and Systems-Level Research to Drive NanotechnologyMichael T. Niemier, Ramprasad Ravichandran, Peter M. Kogge. 302-309 [doi]
- FPGA Emulation of Quantum CircuitsAhmed Usman Khalid, Zeljko Zilic, Katarzyna Radecka. 310-315 [doi]
- 3D Processing Technology and Its Impact on iA32 MicroprocessorsBryan Black, Donald Nelson, Clair Webb, Nick Samra. 316-318 [doi]
- Cache Array Architecture Optimization at Deep Submicron TechnologiesAnnie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutmann. 320-325 [doi]
- Implementation of Fine-Grained Cache Monitoring for Improved SMT SchedulingJoshua L. Kihm, Daniel A. Connors. 326-331 [doi]
- Low Energy, Highly-Associative Cache Design for Embedded ProcessorsAlexander V. Veidenbaum, Dan Nicolaescu. 332-335 [doi]
- The Magic of a Via-Configurable Regular FabricYajun Ran, Malgorzata Marek-Sadowska. 338-343 [doi]
- A Fast Delay Analysis Algorithm for The Hybrid Structured Clock NetworkYi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan. 344-349 [doi]
- Layout Driven Optimization of Datapath Circuits using Arithmetic ReasoningIngmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz. 350-353 [doi]
- Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power & High-SpeedDongku Kang, Hunsoo Choo, Kaushik Roy. 354-357 [doi]
- A Minimal Dual-Core Speculative Multi-Threading ArchitectureSrikanth T. Srinivasan, Haitham Akkary, Tom Holman, Konrad Lai. 360-367 [doi]
- Exploiting Quiescent States in Register LifetimeRama Sangireddy, Arun K. Somani. 368-374 [doi]
- Evaluating Techniques for Exploiting Instruction SlackYau Chin, John Sheu, David Brooks. 375-378 [doi]
- Static Transition Probability Analysis Under UncertaintySiddharth Garg, Siddharth Tata, Ravishankar Arunachalam. 380-386 [doi]
- Circuit-Based Preprocessing of ILP and Its Applications in Leakage Minimization and Power EstimationDonald Chai, Andreas Kuehlmann. 387-392 [doi]
- Analyzing Power Consumption of Message Passing Primitives in a Single-Chip MultiprocessorMirko Loghi, Luca Benini, Massimo Poncino. 393-396 [doi]
- An Architectural Power Estimator for Analog-to-Digital ConvertersZhaohui Huang, Peixin Zhong. 397-400 [doi]
- Formal Hardware Verification based on Signal Correlation PropertiesNikhil Kikkeri, Peter-Michael Seidel. 402-408 [doi]
- Generating Monitor Circuits for Simulation-Friendly GSTE Assertion GraphsKelvin Ng, Alan J. Hu, Jin Yang. 409-416 [doi]
- Graph Automorphism-Based Algorithm for Determining Symmetric InputsChen-Ling Chou, Chun-Yao Wang, Geeng-Wei Lee, Jing-Yang Jou. 417-419 [doi]
- Linear Programming based Techniques for Synthesis of Network-on-Chip ArchitecturesKrishnan Srinivasan, Karam S. Chatha, Goran Konjevod. 422-429 [doi]
- Thermal-Aware IP Virtualization and Placement for Networks-on-Chip ArchitectureWei-Lun Hung, Charles Addo-Quaye, Theo Theocharides, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin. 430-437 [doi]
- Many-to-Many Core-Switch Mapping in 2-D Mesh NoC ArchitecturesChan-Eun Rhee, Han-You Jeong, Soonhoi Ha. 438-443 [doi]
- An Embedded Reconfigurable SIMD DSP with Capability of Dimension-Controllable Vector ProcessingLiang Han, Jie Chen, Chaoxian Zhou, Ying Li, Xin Zhang, Zhibi Liu, Xiaoyun Wei, Baofeng Li. 446-451 [doi]
- Runtime Execution Monitoring (REM) to Detect and Prevent Malicious Code ExecutionA. Murat Fiskiran, Ruby B. Lee. 452-457 [doi]
- Dynamic Address Compression Schemes: A Performance, Energy, and Cost StudyJiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra. 458-463 [doi]
- Compiler-Based Frame Formation for Static OptimizationFeng Shi, Sobeeh Almukhaizim, Pey-Chang Lin, Yiorgos Makris. 466-471 [doi]
- IPC Driven Dynamic Associative Cache Architecture for Low EnergySriram Nadathur, Akhilesh Tyagi. 472-479 [doi]
- Increasing Processor Performance Through Early Register ReleaseOguz Ergin, Deniz Balkan, Dmitry V. Ponomarev, Kanad Ghose. 480-487 [doi]
- Combined Channel Segmentation and Buffer Insertion for Routability and Performance Improvement of FieldHu Huang, Joseph B. Bernstein, Martin Peckerar, Ji Luo. 490-495 [doi]
- Software/Network Co-Simulation of Heterogeneous Industrial Networks ArchitecturesFranco Fummi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino. 496-501 [doi]
- Hardware/Software Co-Modeling of SAT Solver Based on Distributed Computing Elements using SystemCJinwen Xi, Peixin Zhong. 502-504 [doi]
- Coping with The Variability of Combinational Logic DelaysJordi Cortadella, Alex Kondratyev, Luciano Lavagno, Christos P. Sotiriou. 505-508 [doi]
- Design-Space Exploration of Power-Aware On/Off Interconnection NetworksVassos Soteriou, Li-Shiuan Peh. 510-517 [doi]
- Energy Characterization of Hardware-Based Data PrefetchingYao Guo, Saurabh Chheda, Israel Koren, C. Mani Krishna, Csaba Andras Moritz. 518-523 [doi]
- Design and Implementation of Scalable Low-Power Montgomery MultiplierHee-Kwan Son, Sang-Geun Oh. 524-531 [doi]
- Compressed Embedded Diagnosis of Logic CoresScott Ollivierre, Adam B. Kinsman, Nicola Nicolici. 534-539 [doi]
- An Automatic Test Pattern Generation Framework for Combinational Threshold Logic NetworksPallav Gupta, Rui Zhang, Niraj K. Jha. 540-543 [doi]
- An Efficient Algorithm for Reconfiguring Shared Spare RRAMHung-Yau Lin, Hong-Zu Chou, Fu-Min Yeh, Ing-Yi Chen, Sy-Yen Kuo. 544-546 [doi]
- An Accurate Combinatorial Model for Performance Prediction of Deterministic Wormhole Routing in Torus Multicomputer SystemsHashem Hashemi Najaf-abadi, Hamid Sarbazi-Azad. 548-553 [doi]
- Technique to Eliminate Sorting in IP Packet Forwarding DevicesRaymond W. Baldwin, Enrico Ng. 554-559 [doi]
- I/O Clustering in Design Cost and Performance Optimization for Flip-Chip DesignHung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang. 562-567 [doi]
- Placement with Alignment and Performance Constraints Using the B*-Tree RepresentationMeng-Chen Wu, Yao-Wen Chang. 568-571 [doi]
- ACG-Adjacent Constraint Graph for General FloorplansHai Zhou, Jia Wang. 572-575 [doi]