Abstract is missing.
- Soft Errors: Technology Trends, System Effects, and Protection TechniquesSubhasish Mitra, Pia Sanda, Norbert Seifert. 4 [doi]
- Soft-Errors Phenomenon Impacts on Design for Reliability TechnologiesMark Derbey. 7 [doi]
- Accelerating Yield Ramp through Real-Time TestingSanjiv Taneja. 11 [doi]
- Fuse: A Technique to Anticipate Failures due to Degradation in ALUsJaume Abella, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González. 15-22 [doi]
- Design for Resilience to Soft Errors and VariationsMing Zhang, T. M. Mak, James Tschanz, Kee Sup Kim, Norbert Seifert, Davia Lu. 23-28 [doi]
- Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved YieldSomnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia. 29-36 [doi]
- Essential Fault-Tolerance Metrics for NoC InfrastructuresCristian Grecu, Lorena Anghel, Partha Pratim Pande, André Ivanov, Resve Saleh. 37-42 [doi]
- Configurable Error Control Scheme for NoC Signal IntegrityDaniele Rossi, Paolo Angelini, Cecilia Metra. 43-48 [doi]
- An Analytical Model for Reliability Evaluation of NoC ArchitecturesAtefe Dalirsani, Mohammad Hosseinabady, Zainalabedin Navabi. 49-56 [doi]
- An On-Line Fault Detection Scheme for SBoxes in Secure CircuitsGiorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. 57-62 [doi]
- Latchup effect in CMOS IC: a solution for crypto-processors protection against fault injection attacks?N. Buard, F. Miller, C. Ruby, R. Gaillard. 63-70 [doi]
- An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline FoldingOsama Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi. 71-78 [doi]
- Online monitoring of FPGA-based co-processing engines embedded in dependable workstationsNikolaos G. Bartzoudis, Klaus D. McDonald-Maier. 79-84 [doi]
- Methodology and Tools Developed for Validation of COTS-based Fault-Tolerant Spacecraft SupercomputersMichel Pignol. 85-92 [doi]
- Time-Sensitive Control-Flow Checking for Multitask Operating System-Based SoCsFabian Vargas, Leonardo Piccoli, Juliano Benfica, Antonio A. de Alecrim Jr., Marlon Moraes. 93-100 [doi]
- A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex ProcessorsMarta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena. 101-106 [doi]
- A Hybrid Approach to Fault Detection and Correction in SoCsPaolo Bernardi, Leticia Maria Veiras Bolzani, Matteo Sonza Reorda. 107-112 [doi]
- Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUsYannick Monnet, Marc Renaudin, Régis Leveugle. 113-120 [doi]
- Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system designAntonis Papanikolaou, Hua Wang, Miguel Miranda, Francky Catthoor. 121 [doi]
- Infant Mortality--The Lesser Known Reliability IssueT. M. Mak. 122 [doi]
- Circuit Failure Prediction Enables Robust System Design Resilient to Aging and WearoutSubhasish Mitra. 123 [doi]
- Blurring the Layers of Abstractions: Time to Take a Step Back?Krisztián Flautner. 127 [doi]
- Spread in Alpha-Particle-Induced Soft-Error Rate of 90-nm Embedded SRAMsTino Heijmen. 131-136 [doi]
- Multiple Event Transient Induced by Nuclear Reactions in CMOS Logic CellsClaudia Rusu, A. Bougerol, Lorena Anghel, C. Weulersse, N. Buard, S. Benhammadi, N. Renaud, G. Hubert, F. Wrobel, T. Carriere, R. Gaillard. 137-145 [doi]
- Single Event Effects in 1Gbit 90nm NAND Flash Memories under Operating ConditionsM. Bagatin, G. Cellere, Simone Gerardin, Alessandro Paccagnella, A. Visconti, S. Beltrami, M. Maccarrone. 146-151 [doi]
- On Derating Soft Error Probability Based on Strength FilteringAlodeep Sanyal, Sandip Kundu. 152-160 [doi]
- Applicability of Energy Efficient Coding Methodology to Address Signal Integrity in 3D NoC FabricsPartha Pratim Pande, Amlan Ganguly, Brett Feero, Cristian Grecu. 161-166 [doi]
- On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous CircuitsJorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. 167-172 [doi]
- Probabilistic Concurrent Error Compensation in Nonlinear Digital Filters Using Linearized ChecksumsMuhammad Mudassar Nisar, Maryam Ashouei, Abhijit Chatterjee. 173-182 [doi]
- Heavy Ion Test Results in a CMOS triple Voting Register for a High-Energy Physics ExperimentX. Cano, Sebastià A. Bota, R. Graciani, D. Gascón, A. Herms, A. Comerma, Jaume Segura, L. Garrido. 183-184 [doi]
- Robustness of circuits under delay-induced faults : test of AES with the PAFI toolOlivier Faurax, Assia Tria, Laurent Freund, Frédéric Bancel. 185-186 [doi]
- A systematic approach for Failure Modes and Effects Analysis of System-On-ChipsRiccardo Mariani, Gabriele Boschi. 187-188 [doi]
- Highly Reliable Power Aware Memory DesignCostas Argyrides, Dhiraj K. Pradhan. 189-190 [doi]
- Accelerating Soft Error Rate Testing Through Pattern SelectionAlodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu. 191-193 [doi]
- Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon DecodersSalvatore Pontarelli, Luca Sterpone, Gian-Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante. 194-196 [doi]
- Embedding test patterns into Low-Power BIST sequencesIoannis Voyiatzis. 197-198 [doi]
- Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic CodesFabrice Monteiro, Stanislaw J. Piestrak, Houssein Jaber, Abbas Dandache. 199-200 [doi]
- Identification of Critical Errors in Imaging ApplicationsIlia Polian, Damian Nowroth, Bernd Becker. 201-202 [doi]
- Soft Error Rates in 65nm SRAMs--Analysis of new PhenomenaFranz X. Ruckerbauer, Georg Georgakos. 203-204 [doi]
- Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoCMohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale. 205-206 [doi]
- Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test setJimson Mathew, Hafizur Rahaman, Dhiraj K. Pradhan. 207-208 [doi]
- Automated Derivation of Application-aware Error Detectors using Static AnalysisKarthik Pattabiraman, Zbigniew Kalbarczyk, Ravishankar K. Iyer. 211-216 [doi]
- On-Line Self-Healing of Circuits Implemented on Reconfigurable FPGAsManuel G. Gericota, Luís F. Lemos, Gustavo R. Alves, José M. Ferreira. 217-222 [doi]
- A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous CircuitsK. T. Gardiner, Alexandre Yakovlev, Alexandre V. Bystrov. 223-230 [doi]
- Novel Process and Temperature-Stable BICS for Embedded Analog and Mixed-Signal TestJohn Liobe, Martin Margala. 231-236 [doi]
- Envelope Detection Based Transition Time Supervision for Online Testing of RF MEMS SwitchesEmmanuel Simeu, Salvador Mir, R. Kherreddine, H. N. Nguyen. 237-243 [doi]
- Tolerance to Small Delay Defects by Adaptive Clock StretchingSwaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy. 244-252 [doi]
- Statistical Device Variability and its Impact on Yield and PerformanceAsen Asenov. 253 [doi]
- Innovative Design Platforms for Reliable SoCs in Advanced Nanometer TechnologiesDavide Pandini. 254 [doi]
- GRAAL: A Fault-Tolerant Architecture for Enabling Nanometric TechnologiesMichael Nicolaidis. 255 [doi]
- Resilience, Production Yield and Self-Configuration in the Future Massively Defective NanochipsJacques Henri Collet, Piotr Zajac. 259 [doi]
- Surviving to Errors in Multi-Core EnvironmentsXavier Vera, Jaume Abella. 260 [doi]
- Architectural Trade-Offs for Fault Tolerant Multi-Core SystemsKrisztián Flautner. 261 [doi]
- An Automated Methodology for Cogeneration of Test Blocks for Peripheral CoresLeticia Maria Veiras Bolzani, Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero. 265-270 [doi]
- A Functional Self-Test Approach for Peripheral Cores in Processor-Based SoCsAndreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis. 271-276 [doi]
- A Configurable Modular Test Processor and Scan Controller ArchitectureR. Frost Brandenburg, D. Rudolph, Christian Galke, René Kothe, Heinrich Theodor Vierhaus. 277-284 [doi]
- Design of Embedded m-out-of-n Code Checkers Using Complete Parallel CountersSteffen Tarnick. 285-292 [doi]
- LFSR Reseeding with Irreducible PolynomialsSnehal Udar, Dimitri Kagaris. 293-298 [doi]