Table of Contents

• Exploiting Programmable Dipole Interaction in Straintronic Nanomagnet Chains for Ising ProblemsNastaran Darabi, Maeesha Binte Hashem, Supriyo Bandyopadhyay, Amit Ranjan Trivedi. 1 [doi]
• DK Lock: Dual Key Logic Locking Against Oracle-Guided AttacksJordan Maynard, Amin Rezaei 0001. 1-7 [doi]
• Metal Inter-layer Via Keep-out-zone in M3D IC: A Critical Process-aware Design ConsiderationMadhava Sarma Vemuri, Umamaheswara Rao Tida. 1-8 [doi]
• Accurate Estimation of Circuit Delay Variance with Limited Monte Carlo Simulations Using Bayesian InferenceP. R. Chithira. 1-6 [doi]
• Security and Reliability Challenges in Machine Learning for EDA: Latest AdvancesZhiyao Xie, Tao Zhang, Yifeng Peng. 1-6 [doi]
• Using Path Features for Hardware Trojan Detection Based on Machine Learning TechniquesChia-Heng Yen, Jung-Che Tsai, Kai-Chiang Wu. 1-8 [doi]
• Decomposable Architecture and Fault Mitigation Methodology for Deep Learning AcceleratorsNing-Chi Huang, Min-Syue Yang, Ya-chu Chang, Kai-Chiang Wu. 1-8 [doi]
• A Novel Stochastic LSTM Model Inspired by Quantum Machine LearningJoseph Lindsay, Ramtin Zand. 1-8 [doi]
• Design and Evaluation of multipliers for hardware accelerated on-chip EdDSAHarshita Gupta, Mayank Kabra, Nitin D. Patwari, Prashanth H. C., Madhav Rao. 1-9 [doi]
• Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin AccessZhenlin Pei, Mahta Mayahinia, Hsiao-Hsuan Liu, Mehdi B. Tahoori, Shairfe Muhammad Salahuddin, Francky Catthoor, Zsolt Tokei, Chenyun Pan. 1 [doi]
• Testbench on a Chip: A Yield Test Vehicle for Resistive Memory DevicesLuke R. Upton, Guénolé Lallement, Michael D. Scott 0002, Joyce Taylor, Robert M. Radway, Dennis Rich, Mark Nelson, Subhasish Mitra, Boris Murmann. 1-7 [doi]
• Performance Analysis of Cylindrical Through Silicon Via with Interfacial CrackVandana Kumari, Maya Chandrakar, Manoj Kumar Majumder. 1-6 [doi]
• Automatic Subnetwork Search Through Dynamic Differentiable Neuron PruningZigeng Wang, Bingbing Li, Xia Xiao, Tianyun Zhang, Mikhail A. Bragin, Bing Yan, Caiwen Ding, Sanguthevar Rajasekaran. 1-6 [doi]
• Reinforcement Learning-Based Guidance of Autonomous VehiclesJoseph Clemmons, Yu-Fang Jin. 1-6 [doi]
• H-Saber: An FPGA-Optimized Version for Designing Fast and Efficient Post-Quantum Cryptography Hardware AcceleratorsAndrea Guerrieri, Gabriel Da Silva Marques, Francesco Regazzoni 0001, Andres Upegui. 1-6 [doi]
• Dilated Involutional Pyramid Network (DInPNet): A Novel Model for Printed Circuit Board (PCB) Components ClassificationAnanya Mantravadi, Dhruv Makwana, R. Sai Chandra Teja, Sparsh Mittal, Rekha Singhal. 1-7 [doi]
• Focusing on the Key Suspicious Trojan Nets with a Collaborative ApproachShih-Jung Pao, Chuan-Pin Huang, Yen-Chi Peng, Ing-Jer Huang. 1-8 [doi]
• Attributed Graph Transformation for Generating Synthetic Benchmarks for Hardware SecurityJuneet Kumar Meka, Ranga Vemuri. 1-9 [doi]
• Deep Image Segmentation for Defect Detection in Photo-lithography FabricationOmari Paul, Sakib Abrar, Richard Mu, Riadul Islam, Manar D. Samad. 1-7 [doi]
• 2OP: an A* Algorithm OPtimizer with the Heuristic Function for PCB Automatic RoutingQuanbao Guo, Keni Qiu. 1 [doi]
• SQRTLIB : Library of Hardware Square Root DesignsPrashanth H. C., Sriniketh S. S, Shrikrishna Hebbar, Chinmaye R, Madhav Rao. 1-5 [doi]
• eDRAM-OESP: A novel performance efficient in-embedded-DRAM-compute design for on-edge signal processing applicationMayank Kabra, Prashanth H. C., Kedar Deshpande, Madhav Rao. 1-7 [doi]
• VAST: Validation of VP-based Heterogeneous Systems against Availability Security Properties using Static Information Flow TrackingEce Nur Demirhan Coskun, Muhammad Hassan 0002, Mehran Goli, Rolf Drechsler. 1-8 [doi]
• NetViz: A Tool for Netlist Security VisualizationJames Geist, Travis Meade, Shaojie Zhang, Yier Jin. 1-8 [doi]
• A Flexible Cluster Tool Simulation Framework with Wafer Batch Dispatching Time RecommendationHsin-Ping Yen, Shiuan-Hau Huang, Yan-Hsiu Liu, Kuang-Hsien Tseng, Ji-Fu Kung, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang. 1-8 [doi]
• ACPC: Covert Channel Attack on Last Level Cache using Dynamic Cache PartitioningJaspinder Kaur, Shirshendu Das. 1-8 [doi]
• DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN AcceleratorsMahdi Taheri, Mohammad Riazati, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik, Mikael Sjödin, Björn Lisper. 1-8 [doi]
• DSEAdd: FPGA based Design Space Exploration for Approximate Adders with Variable Bit-precisionArchie Mishra, Nanditha Rao. 1-8 [doi]
• Fast Electromigration Simulation for Chip Power GridsBijan Shahriari, Farid N. Najm. 1-8 [doi]
• A Novel Pseudo-Flash Based Digital Low Dropout (LDO) Voltage RegulatorCheng-Yen Lee, Sunil P. Khatri, Sarma B. K. Vrudhula. 1-7 [doi]
• Split-Slope Chaotic Map Providing High Entropy Across Wide RangePartha Sarathi Paul 0002, Maisha Sadia, Anurag Dhungel, Parker Hardy, Md Sakib Hasan. 1-6 [doi]
• AGRAS: Aging and memory request rate aware scheduler for PCM memoriesN. S. Aswathy, Hemangee K. Kapoor. 1-8 [doi]
• Novel, Configurable Approximate Floating-point Multipliers for Error-Resilient ApplicationsVishesh Mishra, Sparsh Mittal, Rekha Singhal, Manoj Nambiar 0001. 1-7 [doi]
• Online Training from Streaming Data with Concept Drift on FPGAsEsther Roorda, Steven J. E. Wilton. 1-8 [doi]
• Power Savings in USB Hubs Through A Proactive Scheduling StrategyBikrant Das Sharma, Abdul Rahman Ismail, Chris Meyers. 1-7 [doi]
• Reverse Engineering Word-Level Models from Look-Up Table NetlistsRam Venkat Narayanan, Aparajithan Nathamuni Venkatesan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri. 1-8 [doi]
• An Optical XNOR-Bitcount Based Accelerator for Efficient Inference of Binary Neural NetworksSairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Ishan G. Thakkar. 1-8 [doi]
• Enlarging Reliable Pairs via Inter-Distance Offset for a PUF Entropy-Boosting AlgorithmMd Omar Faruque, Wenjie Che. 1-8 [doi]
• Design of Hardware Accelerators to Compute Parametric Capacitance TablesSandeep Koranne. 1-8 [doi]
• AGNI: In-Situ, Iso-Latency Stochastic-to-Binary Number Conversion for In-DRAM Deep LearningSupreeth Mysore Shivanandamurthy, Sairam Sri Vatsavai, Ishan G. Thakkar, Sayed Ahmad Salehi. 1-8 [doi]
• Self-Checking Performance Verification Methodology for Complex SoCsProkash Ghosh, V. N. Dwaraka Mai, Aditya Chopra, Baljinder Sood. 1-8 [doi]
• Cryogenic In-memory Binary Multiplier Using Quantum Anomalous Hall Effect MemoriesArun Govindankutty, Shamiul Alam, Sanjay Das, Ahmedullah Aziz, Sumitha George. 1-7 [doi]
• Design Space Exploration of Modular Multipliers for ASIC FHE acceleratorsDeepraj Soni, Mohammed Nabeel 0001, Homer Gamil, Oleg Mazonka, Brandon Reagen, Ramesh Karri, Michail Maniatakos. 1-8 [doi]
• PriML: An Electro-Optical Accelerator for Private Machine Learning on Encrypted DataMengxin Zheng, Fan Chen, Lei Jiang 0001, Qian Lou. 1-7 [doi]
• Analysis of Pattern-dependent Rapid Thermal Annealing Effects on SRAM DesignVidya A. Chhabria, Sachin S. Sapatnekar. 1-7 [doi]
• Moving Towards Game-Changing Technology: Fabrication and Application of HfO2 RRAM for In-Memory ComputingKangjun Bai, Daniel Titcombe, Jack Lombardi, Clare Thiem, Nathaniel Cady. 1-7 [doi]
• Efficient Decryption Architecture for Classic McElieceXinyuan Qiao, Suwen Song, Jing Tian 0004, Zhongfeng Wang 0001. 1-7 [doi]
• High-Throughput Hardware Implementation for Haraka in SPHINCS+Yueqin Dai, Yifeng Song, Jing Tian 0004, Zhongfeng Wang 0001. 1-6 [doi]
• Image-Based Zero-Day Malware Detection in IoMT Devices: A Hybrid AI-Enabled MethodZhangying He, Hossein Sayadi. 1-8 [doi]
• Routability-aware Placement Guidance Generation for Mixed-size DesignsChieh-Yu Cheng, Ting-Chi Wang. 1-7 [doi]
• Error Diluted Approximate Multipliers Using Positive And Negative CompressorsBindu G. Gowda, Prashanth H. C., Madhav Rao. 1-7 [doi]
• Automating Hardware Trojan Detection Using Unsupervised Learning: A Case Study of FPGAShailesh Rajput, Jaya Dofe, Wafi Danesh. 1-6 [doi]
• Heterogeneous Multi-Functional Look-Up-Table-based Processing-in-Memory Architecture for Deep Learning AccelerationSathwika Bavikadi, Purab Ranjan Sutradhar, Amlan Ganguly, Sai Manoj Pudukotai Dinakarrao. 1-8 [doi]
• Low Overhead System-Level Obfuscation through Hardware Resource SharingDaniel Xing, Michael Zuzak, Ankur Srivastava 0001. 1-8 [doi]
• Attacks on Continuous Chaos Communication and Remedies for Resource Limited DevicesRahul Vishwakarma, Ravi Monani, Amin Rezaei 0001, Hossein Sayadi, Mehrdad Aliasgari, Ava Hedayatipour. 1-8 [doi]
• An Area Efficient Superconducting Unary CNN AcceleratorPatricia Gonzalez-Guerrero, Kylie Huch, Nirmalendu Patra, Thom Popovici, George Michelogiannakis. 1-8 [doi]
• Unraveling Latch Locking Using Machine Learning, Boolean Analysis, and ILPDake Chen, Xuan Zhou, Yinghua Hu, Yuke Zhang, Kaixin Yang, Andrew Rittenbach, Pierluigi Nuzzo 0002, Peter A. Beerel. 1-8 [doi]
• Image Quantization Tradeoffs in a YOLO-based FPGA Accelerator FrameworkRichard Yarnell, Mousam Hossain, Ronald F. DeMara. 1-7 [doi]
• An Effective Cost-Skew Tradeoff Heuristic for VLSI Global RoutingAndrew B. Kahng, Shreyas Thumathy, Mingyu Woo. 1-8 [doi]
• MC-MCF: A Multi-Capacity Model for Ordered Escape RoutingZhenyi Gao, Sheqin Dong, Zhicong Tang, Wenjian Yu. 1-7 [doi]
• Quality-driven Design Methodology for PUFs in FPGAs for Secure IoTXiangyun Wang, Yicheng Song, Katyayani Prakash, Zeljko Zilic, Tomas Langsetmo. 1-8 [doi]
• HD2FPGA: Automated Framework for Accelerating Hyperdimensional Computing on FPGAsTinaqi Zhang, Sahand Salamat, Behnam Khaleghi, Justin Morris, Baris Aksanli, Tajana Simunic Rosing. 1-9 [doi]
• Intrinsic Parameter Fluctuation and Process Variation Effect of Vertically Stacked Silicon Nanosheet Complementary Field-Effect TransistorsSekhar Reddy Kola, Yiming Li 0005, Min-Hui Chuang. 1-8 [doi]
• Spiking Domain Feature Extraction with Temporal Dynamic LearningHonghao Zheng, Yang Yi 0002. 1-5 [doi]
• CMDS: Cross-layer Dataflow Optimization for DNN Accelerators Exploiting Multi-bank MemoriesMan Shi, Steven Colleman, Charlotte VanDeMieroop, Antony Joseph, Maurice Meijer, Wim Dehaene, Marian Verhelst. 1-8 [doi]
• Cache Register Sharing Structure for Channel-level Near-memory Processing in NAND Flash MemoryHyunwoo Kim, Hyundong Lee, Jongbeom Kim, Yunjeong Go, Seungwon Baek, Jaehong Song, Junhyeon Kim, Minyoung Jung, Hyodong Kim, Seongju Kim, Taigon Song. 1-6 [doi]
• Knowledge Distillation between DNN and SNN for Intelligent Sensing Systems on Loihi ChipShiya Liu, Yang Yi 0002. 1-8 [doi]
• Resynthesis-based Attacks Against Logic LockingFelipe Almeida, Levent Aksoy, Quang-Linh Nguyen, Sophie Dupuis, Marie-Lise Flottes, Samuel Pagliarini. 1-8 [doi]
• A Low-overhead PUF-based Secure Scan DesignWei Zhou, Aijiao Cui, Cassi Chen, Gang Qu 0001. 1-6 [doi]
• Binary Synaptic Array for Inference and Training with Built-in RRAM Electroforming CircuitAshvinikumar Dongre, Gaurav Trivedi. 1-6 [doi]
• Polymorphic Sensor to Detect Laser Logic State Imaging AttackSourav Roy, Shahin Tajik, Domenic Forte. 1-8 [doi]
• A True Random Number Generator for Probabilistic Computing using Stochastic Magnetic Actuated Random Transducer DevicesAnkit Shukla, Laura Heller, Md Golam Morshed, Laura Rehm, Avik W. Ghosh, Andrew D. Kent, Shaloo Rakheja. 1-10 [doi]
• Neural Network Partitioning for Fast Distributed InferenceRobert Viramontes, Azadeh Davoodi. 1-7 [doi]
• MAAS: Hiding Trojans in Approximate CircuitsQazi Arbab Ahmed, Muhammad Awais 0009, Marco Platzner. 1-6 [doi]
• HIE-DRAM: High Performance Efficient In-DRAM Computing Architecture for SIMDMayank Kabra, Prashanth H. C., Kedar Deshpande, Madhav Rao. 1-7 [doi]
• ISSAC: An Self-organizing and Self-healing MAC Design for Intermittent Communication SystemsRuben Dominguez, Wen Zhang, Hongzhi Xu, Pablo Rangel, Chen Pan. 1-8 [doi]
• Locality-sensing Fast Neural Network (LFNN): An Efficient Neural Network Acceleration Framework via Locality Sensing for Real-time Videos QueriesXiaotian Ma, Jiaqi Tang, Yu Bai. 1-8 [doi]
• XOR-CiM: An Efficient Computing-in-SOT-MRAM Design for Binary Neural Network AccelerationMehrdad Morsali, Ranyang Zhou, Sepehr Tabrizchi, Arman Roohi, Shaahin Angizi. 1-5 [doi]
• Automated Supervised Topic Modeling Framework for Hardware WeaknessesRakibul Hassan, Charan Bandi, Meng-Tien Tsai, Shahriar Golchin, Sai Manoj P. D., Setareh Rafatirad, Soheil Salehi. 1-8 [doi]
• SpotOn: A Gradient-based Targeted Data Poisoning Attack on Deep Neural NetworksYash Khare, Kumud Lakara, Sparsh Mittal, Arvind Kaushik, Rekha Singhal. 1-8 [doi]
• Secure Control Loop Execution of Cyber-Physical Devices Using Predictive State Space ChecksKwondo Ma, Chandramouli N. Amarnath, Abhijit Chatterjee, Jacob A. Abraham. 1-8 [doi]
• DAGGER: Exploiting Language Semantics for Program Security in Embedded SystemsGarret Cunningham, Harsha Chenji, David Juedes, Gordon Stewart 0001, Avinash Karanth. 1-7 [doi]
• Polynomial Formal Verification of a Processor: A RISC-V Case StudyLennart Weingarten, Alireza Mahzoon, Mehran Goli, Rolf Drechsler. 1-7 [doi]
• A Low Power SRAM with Fully Dynamic Leakage Suppression for IoT NodesJun Yin, Mircea R. Stan. 1-8 [doi]
• PreAxC: Error Distribution Prediction for Approximate Computing Quality Control using Graph Neural NetworksLakshmi Sathidevi, Abhinav Sharma, Nan Wu, Xun Jiao, Cong Hao. 1-7 [doi]
• Scalable Low-Cost Sorting Network with Weighted Bit-StreamsBrady Prince, M. Hassan Najafi, Bingzhe Li. 1-6 [doi]
• A SPICE-based Framework to Emulate Quantum Circuits with classical LC ResonatorsMd. Mazharul Islam 0006, Md. Shafayat Hossain, Ahmedullah Aziz. 1-7 [doi]
• Accounting for Floorplan Irregularity and Configuration Dependence in FPGA Routing Delay ModelsGabriel Barajas, Jonathan W. Greene, Fei Li, James Tandon. 1-6 [doi]
• A Novel Scalable Array Design for III-V Compound Semiconductor-based Nonvolatile Memory (UltraRAM) with Separate Read-Write PathsShamiul Alam, Kazi Asifuzzaman, Ahmedullah Aziz. 1-7 [doi]
• RECO-LFSR: Reconfigurable Low-power Cryptographic processor based on LFSR for Trusted IoT platformsMohamed El-Hadedy 0001, Russell Hua, Kazutomo Yoshii, Wen-mei Hwu, Martin Margala. 1-7 [doi]
• ZOCHEN: Compression Using Zero Chain Elimination and Encoding to Improve Endurance of Non-Volatile MemoriesNishant Bharti, Arijit Nath, Swati Upadhyay, Hemangee K. Kapoor. 1-8 [doi]
• A Deep Learning Approach for Ventricular Arrhythmias Classification using MicrocontrollerYa-sine Agrignan, Shanglin Zhou, Jun Bai, Sahidul Islam, Sheida Nabavi, Mimi Xie, Caiwen Ding. 1-5 [doi]
• TOTAL: Topology Optimization of Operational Amplifier via Reinforcement LearningZihao Chen, Songlei Meng, Fan Yang 0001, Li Shang, Xuan Zeng 0001. 1-8 [doi]
• Application of Machine Learning for Quality Risk Factor Analysis of Electronic AssembliesBrendan Reidy, David Duggan, Bernard Glasauer, Peng Su, Ramtin Zand. 1-6 [doi]
• DC-Model: A New Method for Assisting the Analog Circuit OptimizationYuan Wang, Jian-xin, Haixu Liu, Qian Qin, Chenkai Chai, Yukai Lu, Jinglei Hao, Jianhao Xiao, Zuochang Ye, Yan Wang. 1-7 [doi]
• Novel Implementation of High-Performance Polynomial Multiplication for Unified KEM Saber based on TMVP Design StrategyPengzhou He, Jiafeng Xie. 1-8 [doi]
• CMP-SiL: Confidential Multi Party Software-in-the-Loop Simulation FrameworksShalabh Jain, Pradeep Pappachan, Jorge Guajardo, Sven Trieflinger, Indrasen Raghupatruni, Thomas Huber. 1-8 [doi]
• A Polymorphic Electro-Optic Logic Gate for High-Speed Reconfigurable Computing CircuitsVenkata Sai Praneeth Karempudi, Sairam Sri Vatsavai, Ishan G. Thakkar, Jeffrey Todd Hastings. 1-8 [doi]
• A Bit-Parallel Deterministic Stochastic MultiplierSairam Sri Vatsavai, Ishan G. Thakkar. 1 [doi]
• SPRED: Spatially Distributed Laser Fault Injection Resilient DesignTasnuva Farheen, Shahin Tajik, Domenic Forte. 1-8 [doi]
• Lightweight Instruction Set for Flexible Dilated Convolutions and Mixed-Precision OperandsSimon Friedrich, Shambhavi Balamuthu Sampath, Robert Wittig, Manoj Rohit Vemparala, Nael Fasfous, Emil Matús, Walter Stechele, Gerhard P. Fettweis. 1-8 [doi]
• A Novel Method Against Hardware Trojans in Approximate CircuitsYuqin Dou, Chongyan Gu, Chenghua Wang, Weiqiang Liu 0001. 1-6 [doi]
• Hardware Performance Counter Enhanced Watchdog for Embedded Software SecurityKarl Ott, Rabi N. Mahapatra. 1-8 [doi]
• On-Interposer Decoupling Capacitors Placement for Interposer-based 3DICPo-Yang Chen, Chang-Yun Liu, Hung-Ming Chen, Po-Tsang Huang. 1-6 [doi]
• Analysis of Machine Learning Techniques for Time Domain Waveform Prediction in Analog and Mixed Signal Integrated Circuit VerificationDhanasekar V, Vinodhini Gunasekaran, Anusha Challa, Bama Srinivasan, J. Dhurga Devi, Selvi Ravindran, Ranjani Parthasarathi, P. V. Ramakrishna, Gopika Geetha Kumar, Venkateswaran Padmanabhan, Guha Lakshmanan, Lakshmanan Balasubramanian. 1-9 [doi]
• Reproducing Fear Conditioning of Rats with Unmanned Ground Vehicles and Neuromorphic SystemsNoah Zins, Hongyu An. 1-7 [doi]
• HFGCN: High-speed and Fully-optimized GCN AcceleratorMinseok Han, Jiwan Kim, Donggeon Kim, Hyunuk Jeong, Gilho Jung, Myeongwon Oh, Hyundong Lee, Yunjeong Go, Hyunwoo Kim, Jongbeom Kim, Taigon Song. 1-7 [doi]