Abstract is missing.
- Hardware in loop testing of an insulin pumpSriram Karunagaran, Karuna P. Sahoo, Masahiro Fujita. 1-8 [doi]
- Contactless pre-bond TSV fault diagnosis using duty-cycle detectors and ring oscillatorsSergej Deutsch, Krishnendu Chakrabarty. 1-10 [doi]
- Testing methods for quaternary content addressable memory using charge-sharing sensing schemeHao-Yu Yang, Rei-Fu Huang, Chin-Lung Su, Kuan-Hong Lin, Hang-Kaung Shu, Chi-Wei Peng, Mango Chia-Tso Chao. 1-10 [doi]
- A DLL-based test solution for through silicon via (TSV) in 3D-stacked ICsRashid Rashidzadeh, Esrafil Jedari, Tareq Muhammad Supon, Vladimir Mashkovtsev. 1-9 [doi]
- A deterministic BIST scheme based on EDT-compressed test patternsGrzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jedrzej Solecki, Jerzy Tyszer. 1-8 [doi]
- Embedded deterministic test points for compact cell-aware testsCesar Acero, Derek Feltham, Friedrich Hapke, Elham K. Moghaddam, Nilanjan Mukherjee, Vidya Neerkundar, Marek Patyra, Janusz Rajski, Jerzy Tyszer, Justyna Zawada. 1-8 [doi]
- Generalization of an outlier model into a "global" perspectiveSebastian Siatkowski, Chia-Ling Chang, Li-C. Wang, Nikolas Sumikawa, LeRoy Winemberg, W. Robert Daasch. 1-10 [doi]
- Cross-layer approaches for an aging-aware design of nanoscale microprocessors: Dissertation summary: IEEE TTTC E.J. McCluskey doctoral thesis award competition finalistFabian Oboril, Mehdi Baradaran Tahoori. 1-10 [doi]
- A structured approach to post-silicon validation and debug using symbolic quick error detectionDavid Lin, Eshan Singh, Clark Barrett, Subhasish Mitra. 1-10 [doi]
- Automated testing of bare die-to-die stacksErik Jan Marinissen, Bart De Wachter, Teng Wang, Jens Fiedler, Jorg Kiesewetter, Karsten Stoll. 1-10 [doi]
- A comparative study of one-shot statistical calibration methods for analog / RF ICsYichuan Lu, Kiruba S. Subramani, He Huang, Nathan Kupp, Ke Huang, Yiorgos Makris. 1-10 [doi]
- Efficient observation-point insertion for diagnosability enhancement in digital circuitsZipeng Li, Sandeep Kumar Goel, Frank Lee, Krishnendu Chakrabarty. 1-10 [doi]
- Secure design-for-debug for Systems-on-ChipJerry Backer, David Hély, Ramesh Karri. 1-8 [doi]
- Rapid prototyping and test before silicon of integrated pressure sensorsAdrian I. Voinea, Stefan Kampfer. 1-9 [doi]
- A general testing method for digital microfluidic biochips under physical constraintsTrung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, Krishnendu Chakrabarty. 1-8 [doi]
- eRNA: Refining of reconstructed digital waveformHideo Okawara. 1-10 [doi]
- Monitoring the delay of long interconnects via distributed TDCMeng-Ting Tsai, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng. 1-9 [doi]
- Streaming fast access to ADCs and DACs for mixed-signal ATPGStephen Sunter, J.-F. Cote, Jeff Rearick. 1-8 [doi]
- Platform IO and system memory test using L3 cache based test (CBT) and parallel execution of CPGC Intel BIST engineBruce Querbach, Tan Peter Yanyang, Lovelace Van, David Blankenbeckler, Rahul Khanna, Sudeep Puligundla, Patrick Chiang. 1-10 [doi]
- A new method for measuring alias-free aperture jitter in an ADC outputTakahiro J. Yamaguchi, Katsuhiko Degawa, Masayuki Kawabata, Masahiro Ishida, Koichiro Uekusa, Mani Soma. 1-6 [doi]
- Access time minimization in IEEE 1687 networksRene Krenz-Baath, Farrokh Ghani Zadegan, Erik Larsson. 1-10 [doi]
- Electrical package defect testing for volume productionXue Ming, Koelz Johann, Lee Chow York, Lee Kwan Wee, Shi Zhi Min. 1-9 [doi]
- PiRA: IC authentication utilizing intrinsic variations in pin resistanceAbhishek Basak, Fengchao Zhang, Swarup Bhunia. 1-8 [doi]
- Developing a modern platform for test engineering - Introducing the origen semiconductor developer's kitStephen McGinty, Daniel Hadad, Chris Nappi, Brian Caquelin. 1-10 [doi]
- A self-compensating built-in self-test solution for RF phased array mismatchJae-woong Jeong, Jennifer Kitchen, Sule Ozev. 1-9 [doi]
- Concurrent hardware Trojan detection in wireless cryptographic ICsYu Liu, Georgios Volanis, Ke Huang, Yiorgos Makris. 1-8 [doi]
- Optimizing delay tests at the memory boundaryKelly A. Ockunzzi, Michael R. Ouellette, Kevin W. Gorman. 1-9 [doi]
- Test and debug solutions for 3D-stacked integrated circuitsSergej Deutsch, Krishnendu Chakrabarty. 1-10 [doi]
- Tolerance analysis of fixture fabrication, from drilling holes to pointing accuracyAn-Jim Long, David Tsai, Kent Lien, Steve Hsu. 1-4 [doi]
- Design reflection for optimal test-chip implementationR. D. (Shawn) Blanton, Benjamin Niewenhuis, Zeye Dexter Liu. 1-10 [doi]
- Information-theoretic and statistical methods of failure log selection for improved diagnosisSarmad Tanwir, Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan. 1-10 [doi]
- Evaluation of low-cost mixed-signal test techniques for circuits with long simulation timesHaralampos-G. D. Stratigopoulos, Manuel J. Barragan, Salvador Mir, Herve Le Gall, Neha Bhargava, Ankur Bal. 1-7 [doi]
- An ATE system for testing 2.4-GHz RF digital communication devices with QAM signal interfacesMasahiro Ishida, Kiyotaka Ichiyama. 1-9 [doi]
- Yield and reliability enhancement for 3D ICs: Dissertation summary: IEEE TTTC E.J. McCluskey doctoral thesis award competition finalistLi Jiang, Qiang Xu. 1-11 [doi]
- Extending residue-based fault tolerance to encrypted computationNektarios Georgios Tsoutsos, Michail Maniatakos. 1-10 [doi]
- A case study: Leverage IEEE 1687 based method to automate modeling, verification, and test access for embedded instruments in a server processorTassanee Payakapan, Senwen Kan, Ken Pham, Kathy Yang, J.-F. Cote, Martin Keim, Jennifer Dworak. 1-10 [doi]
- How many probes is enough? A low cost method for probe card depopulation with low riskKevin Tiernan, Snehamay Sinha, Lily Pang, Robert Williams, Ken Delling. 1-5 [doi]
- On generating high quality tests based on cell functionsXijiang Lin, Sudhakar M. Reddy. 1-9 [doi]
- Stochastic timing error rate estimation under process and temporal variationsShoichi Iizuka, Yutaka Masuda, Masanori Hashimoto, Takao Onoye. 1-10 [doi]
- Test-access-mechanism optimization for multi-Vdd SoCsFotios Vartziotis, Xrysovalantis Kavousianos, Panagiotis Georgiou, Krishnendu Chakrabarty. 1-10 [doi]
- Stepped parity: A low-cost multiple bit upset detection techniqueMojtaba Ebrahimi, Mehdi Baradaran Tahoori. 1-8 [doi]
- AdaTest: An efficient statistical test framework for test escape screeningFan Lin, Chun-Kai Hsu, Kwang-Ting Cheng. 1-8 [doi]
- On diagnosable and tunable 3D clock network design for lifetime reliability enhancementLi Jiang, Pu Pang, Naifeng Jing, Sung Kyu Lim, Xiaoyao Liang, Qiang Xu. 1-10 [doi]
- FASTrust: Feature analysis for third-party IP trust verificationSong Yao, Xiaoming Chen, Jie Zhang, Qiaoyi Liu, Jia Wang, Qiang Xu, Yu Wang, Huazhong Yang. 1-10 [doi]
- Hardware Trojans hidden in RTL don't cares - Automated insertion and prevention methodologiesNicole Fern, Shrikant Kulkarni, Kwang-Ting (Tim) Cheng. 1-8 [doi]
- Brain-inspired computingKarim Arabi. 7 [doi]
- Modeling the future of semiconductors (and test!)Andrew B. Kahng. 8 [doi]
- Can we ensure reliability in the era of heterogeneous integration?William R. Bottoms. 9 [doi]