Table of Contents

• A Fast and Low Cost Embedded Test Solution for CMOS Image SensorsJ. Lefevre, Philippe Debaud, P. Girard, Arnaud Virazel. 1-9 [doi]
• ACE-Pro: Reduction of Functional Errors with ACE Propagation GraphDun-An Yang, Yu-Teng Chang, Ting-Shuo Hsu, Jing-Jia Liou, Harry H. Chen. 10-19 [doi]
• Testability-Enhancing Resynthesis of Reconfigurable Scan NetworksNatalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich. 20-29 [doi]
• Adaptive NN-based Root Cause Analysis in Volume Diagnosis for Yield ImprovementXin Huang, Min Qin, Ruosheng Xu, Cheng Chen, Shangling Jui, Zhihao Ding, Pengyun Li, Yu Huang. 30-36 [doi]
• Machine Learning for Circuit Aging Estimation under Workload DependencyFlorian Klemme, Hussam Amrouch. 37-46 [doi]
• Minimum Operating Voltage Prediction in Production Test Using Accumulative LearningYen-Ting Kuo, Wei-Chen Lin, Chun Chen, Chao-Ho Hsieh, James Chien-Mo Li, Eric Jia-Wei Fang, Sung S.-Y. Hsueh. 47-52 [doi]
• Smart Sampling for Efficient System Level Test: A Robust Machine Learning ApproachChenwei Liu, Jie Ou. 53-62 [doi]
• The Security Enhancement Techniques of the Double-layer PUF Against the ANN-based Modeling AttackYongliang Chen, Xiaole Cui, Wenqiang Ye, Xiaoxin Cui. 63-72 [doi]
• ∗Arjun Chaudhuri, Ching-Yuan Chen, Jonti Talukdar, Siddarth Madala, Abhishek Kumar Dubey, Krishnendu Chakrabarty. 73-82 [doi]
• On-line Functional Testing of Memristor-mapped Deep Neural Networks using Backdoored ChecksumsChing-Yuan Chen, Krishnendu Chakrabarty. 83-92 [doi]
• Efficient Functional In-Field Self-Test for Deep Learning AcceleratorsYi He, Takumi Uezono, Yanjing Li. 93-102 [doi]
• Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian ProcessMichihiro Shintani, Riaz-ul-haque Mian, Michiko Inoue, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki. 103-112 [doi]
• Semi-supervised Wafer Map Pattern Recognition using Domain-Specific Data Augmentation and Contrastive LearningHanbin Hu, Chen He, Peng Li 0001. 113-122 [doi]
• Brain-Inspired Computing for Wafer Map Defect Pattern ClassificationPaul R. Genssler, Hussam Amrouch. 123-132 [doi]
• Study on High-Accuracy and Low-Cost Recycled FPGA DetectionFoisal Ahmed, Michihiro Shintani, Michiko Inoue. 133-142 [doi]
• Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test SolutionsLizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui. 143-152 [doi]
• Adaptive Methods for Machine Learning-Based Testing of Integrated Circuits and BoardsMengyun Liu, Krishnendu Chakrabarty. 153-162 [doi]
• Impeccable Circuits IIIShahram Rasoolzadeh, Aein Rezaei Shahmirzadi, Amir Moradi 0001. 163-169 [doi]
• *Jonti Talukdar, Siyuan Chen, Amitabh Das, Sohrab Aftabjahani, Peilin Song, Krishnendu Chakrabarty. 170-179 [doi]
• LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted EnvironmentM. Sazadur Rahman, Henian Li, Rui Guo, Fahim Rahman, Farimah Farahmandi, Mark Mohammad Tehranipoor. 180-189 [doi]
• MINiature Interactive Offset Networks (MINIONs) for Wafer Map ClassificationYueling Jenny Zeng, Li-C. Wang, Chuanhe Jay Shan. 190-199 [doi]
• Triplet Convolutional Networks for Classifying Mixed-Type WBM Patterns with Noisy LabelsChenwei Liu, Qiaoyue Tang. 200-207 [doi]
• Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced LabelingLeon Li-Yang Chen, Katherine Shu-Min Li, Xu-Hao Jiang, Sying-Jyan Wang, Andrew Yi-Ann Huang, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu. 208-212 [doi]
• Characterizing Corruptibility of Logic Locks using ATPGDanielle Duvalsaint, R. D. Shawn Blanton. 213-222 [doi]
• SymbA: Symbolic Execution at C-level for Hardware Trojan ActivationArash Vafaei, Nick Hooten, Mark Tehranipoor, Farimah Farahmandi. 223-232 [doi]
• Open-short Normalization Method for a Quick Defect Identification in Branched Traces with High-resolution Time-domain ReflectometryYang Shang, Makoto Shinohara, Eiji Kato, Masaichi Hashimoto, Joanna Kiljan. 233-242 [doi]
• Relevant Signals and Devices for Failure Analysis of Analog and Mixed-signal CircuitsTommaso Melis, Emmanuel Simeu, Luc Saury, Etienne Auvray. 243-250 [doi]
• Improving Volume Diagnosis and Debug with Test Failure Clustering and ReorganizationMu-Ting Wu, Cheng-Sian Kuo, James Chien-Mo Li, Chris Nigh, Gaurav Bhargava. 251-259 [doi]
• On Reduction of Deterministic Test Pattern SetsStephan Eggersglüß, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer. 260-267 [doi]
• Analyzing and Mitigating Sensing Failures in Spintronic-based Computing in MemoryMahta Mayahinia, Christopher Münch, Mehdi B. Tahoori. 268-277 [doi]
• Multi-Transition Fault Model (MTFM) ATPG patterns towards achieving 0 DPPB on automotive designsJorge Corso, Saidapet Ramesh, Kumar Abishek, Ley Teng Tan, Chik Hooi Lew. 278-283 [doi]
• Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling FrequenciesKeno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jianglin Wei, Takayuki Nakatani, Yujie Zhao, Shogo Katayama, Shuhei Yamamoto, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi 0001. 284-288 [doi]
• Adaptive High Voltage Stress Methodology to Enable Automotive Quality on FinFET TechnologiesStephen Traynor, Chen He, Y. Y. Yu, Ken Klein. 289-293 [doi]
• 3.5Gsps MIPI C-PHY Receiver Circuit for Automatic Test EquipmentSeongkwan Lee, Minho Kang, Cheolmin Park, HyungSun Ryu, Jaemoo Choi, Byunghyun Yim. 294-298 [doi]
• A Scalable Design Flow for Performance Monitors Using Functional Path Ring OscillatorsTobias Kilian, Heiko Ahrens, Daniel Tille, Martin Huch, Ulf Schlichtmann. 299-303 [doi]
• Systematic Hardware Error Identification and Calibration for Massive Multisite TestingPraise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abdullah O. Obaidi, Abalhassan Sheikh, Srivaths Ravi 0001, Degang Chen. 304-308 [doi]
• WGrid: Wafermap Grid Pattern Recognition with Machine Learning TechniquesPeter Yi-Yu Liao, Katherine Shu-Min Li, Leon Li-Yang Chen, Sying-Jyan Wang, Andrew Yi-Ann Huang, Ken Chau-Cheung Cheng, Nova Cheng-Yen Tsai, Leon Chou. 309-313 [doi]
• AAA: Automated, On-ATE AI Debug of Scan Chain FailuresChris Nigh, Gaurav Bhargava, Ronald D. Blanton. 314-318 [doi]
• Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture BitsYi Sun, Hui Jiang, Lakshmi Ramakrishnan, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, R. Iris Bahar. 319-323 [doi]
• Testability-Aware Low Power Controller Design with Evolutionary LearningMin Li, Zhengyuan Shi, Zezhong Wang, Weiwei Zhang, Yu Huang, Qiang Xu. 324-328 [doi]
• An automated formal-based approach for reducing undetected faults in ISO 26262 hardware compliant designsFelipe Augusto da Silva, Ahmet Cagri Bagbaba, Said Hamdioui, Christian Sauer 0001. 329-333 [doi]
• Is your secure test infrastructure secure enough? : Attacks based on delay test patterns using transient behavior analysisSergej Meschkov, Dennis R. E. Gnad, Jonas Krautter, Mehdi B. Tahoori. 334-338 [doi]
• Seamless Physical Implementation of ASIC Hierarchical Integrated Scan ArchitectureBambang Suparjo, Jugantor Chetia, Ankit R. Shah. 339-343 [doi]
• Security EDA Extension through P1687.1 and 1687 CallbacksMichele Portolan, Vincent Reynaud, Paolo Maistri, Régis Leveugle, Giorgio Di Natale. 344-353 [doi]
• Accessing general IEEE Std. 1687 networks via functional portsErik Larsson, Prathamesh Murali, Ziling Zhang. 354-363 [doi]
• Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio AnalyzerDaisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Akemi Hatta, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jianglin Wei, Yujie Zhao, Minh Tri Tran, Kazumi Hatayama, Haruo Kobayashi 0001. 364-373 [doi]
• Automatic Verification of Mixed-Signal ATE Test Programs using Device VariationFranziska Mayer, Christian Schott, Enrico Billich, Saeid Yazdani, Ulrich Heinkel, Georg Daler, Bernhard Ruf, Ricardo Pannuzzo, Wolfgang Dickenscheid. 374-379 [doi]
• Background Receiver IQ Imbalance Correction for in-Field and Post-Production Testing and CalibrationMuslum Emir Avci, Sule Ozev. 380-388 [doi]
• Hierarchical Failure Modeling and Machine Learning Assisted Correction of Electro-Mechanical Subsystem Failures in Autonomous VehiclesChandramouli N. Amarnath, Md Imran Momtaz, Abhijit Chatterjee. 389-398 [doi]
• Exploiting Application Tolerance for Functional SafetyV. Prasanth, Rubin A. Parekhji, Bharadwaj Amrutur. 399-408 [doi]
• Compositional Fault Propagation Analysis in Embedded Systems using Abstract InterpretationChristian Bartsch, Stephan Wilhelm, Daniel Kästner, Dominik Stoffel, Wolfgang Kunz. 409-418 [doi]