Michael S. Schlansker - researchr alias

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Viewing Publication 1 - 34 from 34

2013

Configurable optical interconnects for scalable datacentersMichael S. Schlansker, Michael R. T. Tan, Jean Tourrilhes, Jose Renato Santos, Shih-Yuan Wang. ofc 2013: 1-3 [doi]

2007

High-performance ethernet-based communications for future multi-core processorsMichael S. Schlansker, Nagabhushan Chitlur, Erwin Oertli, Paul M. Stillwell Jr., Linda Rankin, Dennis Bradford, Richard J. Carter, Jayaram Mudigonda, Nathan L. Binkert, Norman P. Jouppi. sc 2007: 37 [doi]

2006

Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast BarriersJack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker, Brad Calder. micro 2006: 235-246 [doi]

2005

Fast synchronization for chip multiprocessorsJack Sampson, Ruben Gonzalez, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker. sigarch, 33(4):64-69, 2005. [doi]

A Distributed Control Path Architecture for VLIW ProcessorsHongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael S. Schlansker. IEEEpact 2005: 197-206 [doi]

2003

In Memory of Bob RauMichael S. Schlansker. euromicro 2003: 165-168 [doi]

2001

2000

Embedded Computing: New Directions in Architecture and AutomationB. Ramakrishna Rau, Michael S. Schlansker. hipc 2000: 225-244 [doi]

EPIC: Explicititly Parallel Instruction ComputingMichael S. Schlansker, B. Ramakrishna Rau. Computer, 33(2):37-45, 2000. [doi]

1999

Control CPR: A Branch Height Reduction Optimization for EPIC ArchitecturesMichael S. Schlansker, Scott A. Mahlke, Richard Johnson. PLDI 1999: 155-168 [doi]

1997

1996

1995

Spill-free parallel scheduling of basic blocksB. Natarajan, Michael S. Schlansker. euromicro 1995: 119-124 [doi]

Critical path reduction for scalar programsMichael S. Schlansker, Vinod Kathail. euromicro 1995: 57-69 [doi]

1994

Height reduction of control recurrences for ILP processorsMichael S. Schlansker, Vinod Kathail, Sadun Anik. euromicro 1994: 40-51 [doi]

1993

Sentinel Scheduling for VLIW and Superscalar ProcessorsScott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker. tocs, 11(4):376-408, 1993. [doi]

Acceleration of First and Higher Order Recurrences on Processors with Instruction Level ParallelismMichael S. Schlansker, Vinod Kathail. lcpc 1994: 406-429

1992

Sentinel Scheduling for VLIW and Superscalar ProcessorsScott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker. asplos 1992: 238-247

Register Allocation for Software Pipelined LoopsB. Ramakrishna Rau, M. Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker. PLDI 1992: 283-299

Code generation schema for modulo scheduled loopsB. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai. euromicro 1992: 158-169 [doi]

1991

Parallelization of WHILE loops on pipelined architecturesParthasarathy P. Tirumalai, Meng Lee, Michael S. Schlansker. tjs, 5(2-3):119-136, 1991. [doi]

1990

Parallelization of loops with exits on pipelined architecturesParthasarathy P. Tirumalai, M. Lee, Michael S. Schlansker. sc 1990: 200-212 [doi]

1989

The Cydram 5 Stride-Insensitive Memory SystemB. Ramakrishna Rau, Michael S. Schlansker, David W. L. Yen. icpp 1989: 242-246

1982

Systematically derived instruction sets for high-level language supportPradip Bose, B. Ramakrishna Rau, Michael S. Schlansker. ACMse 1982: 73-84 [doi]

1973

A microprogramming language for the B-1726David J. DeWitt, Michael S. Schlansker, Daniel E. Atkins. micro 1973: 21-29 [doi]

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