Tse-Yu Yeh - researchr alias

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Viewing Publication 1 - 17 from 17

2016

Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC ProcessorOnur Mutlu, Rich Belgard, Thomas R. Gross, Norman P. Jouppi, John L. Hennessy, Steven A. Przybylski, Chris Rowen, Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Tse-Yu Yeh, Andy Wolfe. micro, 36(4):70-85, 2016. [doi]

2014

Author retrospective for increasing the instruction fetch rate via multiple branch prediction and a branch address cacheTse-Yu Yeh, Deborah T. Marr, Yale N. Patt. ics 2014: 24-25 [doi]

2007

Low-Power, High-Performance Architecture of the PWRficient Processor FamilyTse-Yu Yeh. micro, 27(2):69-78, 2007. [doi]

2006

Low-power, high-performance architecture of the PWRficient processor familyTse-Yu Yeh. hotchips 2006: 1-29 [doi]

2001

Understanding branches and designing branch predictors for high-performance microprocessorsMarius Evers, Tse-Yu Yeh. pieee, 89(11):1610-1620, 2001. [doi]

1998

Retrospective: Alternative Implementations of Two-Level Adaptive Training Branch PredictionTse-Yu Yeh, Yale N. Patt. isca 1998: 87-88 [doi]

Alternative Implementations of Two-Level Adaptive Branch PredictionTse-Yu Yeh, Yale N. Patt. isca 1998: 451-461 [doi]

1996

Branch Classification: New Mechanism for Improving Branch Predictor PerformancePo-Yung Chang, Eric Hao, Tse-Yu Yeh, Yale N. Patt. ijpp, 24(2):133-158, 1996.

1994

Branch classification: a new mechanism for improving branch predictor performancePo-Yung Chang, Eric Hao, Tse-Yu Yeh, Yale N. Patt. euromicro 1994: 22-31 [doi]

1993

Two-level adaptive branch prediction and instruction fetch mechanisms for high performance superscalar processorsTse-Yu Yeh. PhD thesis, University of Michigan, USA, 1993. [doi]

Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processorsTse-Yu Yeh, Yale N. Patt. euromicro 1993: 164-175 [doi]

Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address CacheTse-Yu Yeh, Deborah T. Marr, Yale N. Patt. ics 1993: 67-76 [doi]

A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch HistoryTse-Yu Yeh, Yale N. Patt. isca 1993: 257-266

1992

A comprehensive instruction fetch mechanism for a processor supporting speculative executionTse-Yu Yeh, Yale N. Patt. euromicro 1992: 129-139 [doi]

Alternative Implementations of Two-Level Adaptive Branch PredictionTse-Yu Yeh, Yale N. Patt. isca 1992: 124-134

1991

Single Instruction Stream Parallelism is Greater Than TwoMichael Butler, Tse-Yu Yeh, Yale N. Patt, Mitch Alsup, Hunter Scales, Michael Shebanow. isca 1991: 276-286 [doi]

Two-Level Adaptive Training Branch PredictionTse-Yu Yeh, Yale N. Patt. micro 1991: 51-61 [doi]

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