Yukihito Oowaki - researchr alias

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Viewing Publication 1 - 18 from 18

2015

Caching mechanisms towards single-level storage systems for Internet of ThingsYosuke Bando, Konosuke Watanabe, Ken-ichi Maeda, Hiroki Kudo, Masahiro Ishiyama, Atsushi Kunimatsu, Hiroto Nakai, Masafumi Takahashi, Yukihito Oowaki. vlsic 2015: 132 [doi]

2014

An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal ProcessingDaisuke Miyashita, Ryo Yamaki, Kazunori Hashiyoshi, Hiroyuki Kobayashi, Shouhei Kousai, Yukihito Oowaki, Yasuo Unekawa. jssc, 49(1):73-83, 2014. [doi]

19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extensionKonosuke Watanabe, Kenichiro Yoshii, Nobuhiro Kondo, Kenichi Maeda, Toshio Fujisawa, Junji Wadatsumi, Daisuke Miyashita, Shouhei Kousai, Yasuo Unekawa, Shinsuke Fujii, Takuma Aoyama, Takayuki Tamura, Atsushi Kunimatsu, Yukihito Oowaki. isscc 2014: 330-331 [doi]

A UHS-II SD card controller with 240MB/s write throughput and 260MB/s read throughputKenta Yasufuku, Naoto Oshiyama, Toshitada Saito, Yukimasa Miyamoto, Yutaka Nakamura, Ryota Terauchi, Atsushi Kondo, Takuma Aoyama, Masafumi Takahashi, Yukihito Oowaki, Ryoichi Bandai. asscc 2014: 29-32 [doi]

2013

A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processingDaisuke Miyashita, Ryo Yamaki, Kazunori Hashiyoshi, Hiroyuki Kobayashi, Shouhei Kousai, Yukihito Oowaki, Yasuo Unekawa. isscc 2013: 420-421 [doi]

2011

2010

A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nmYu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Yukihito Oowaki. isscc 2010: 326-327 [doi]

2007

An automated runtime power-gating schemeMototsugu Hamada, Takeshi Kitahara, Naoyuki Kawabe, Hironori Sato, Tsuyoshi Nishikawa, Takayoshi Shimazawa, Takahiro Yamashita, Hiroyuki Hara, Yukihito Oowaki. iccd 2007: 382-387 [doi]

2006

2005

A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSIMototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Chen Kong Teh, Takayoshi Shimazawa, Naoyuki Kawabe, Takeshi Kitahara, Yu Kikuchi, Tsuyoshi Nishikawa, Makoto Takahashi, Yukihito Oowaki. cicc 2005: 527-530 [doi]

2001

A 76-mm/sup 2/ 8-Mb chain ferroelectric memoryDaisaburo Takashima, Yoshiaki Takeuchi, Tadashi Miyakawa, Yasuo Itoh, Ryu Ogiwara, Masahiro Kamoshida, Katsuhiko Hoya, Sumiko Mano Doumae, Tohru Ozaki, Hiroyuki Kanaya, Koji Yamakawa, Iwao Kunishima, Yukihito Oowaki. jssc, 36(11):1713-1720, 2001. [doi]

1999

A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line driveDaisaburo Takashima, Susumu Shuto, Iwao Kunishima, Hiroyuki Takenaka, Yukihito Oowaki, Shin'ichi Tanaka. jssc, 34(11):1557-1563, 1999. [doi]

1998

Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI'sDaisaburo Takashima, Yukihito Oowaki, Shigeyoshi Watanabe, Kazunori Ohuchi. jssc, 33(2):260-267, 1998. [doi]

1997

A novel power-off mode for a battery-backup DRAMDaisaburo Takashima, Yukihito Oowaki. jssc, 32(1):86-91, 1997. [doi]

1994

Open/folded bit-line arrangement for ultra-high-density DRAM'sDaisaburo Takashima, Shigeyoshi Watanabe, Hiroaki Nakano, Yukihito Oowaki, Kazunori Ohuchi. jssc, 29(4):539-542, April 1994. [doi]

Standby/active mode logic for sub-1-V operating ULSI memoryDaisaburo Takashima, Shigeyoshi Watanabe, Hiroalu Nakano, Yukihito Oowaki, Kazunori Ohuchi, Hiroyuki Tango. jssc, 29(4):441-447, April 1994. [doi]

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