Abstract is missing.
- Multi-Site Collaboration in System on Chip Design and Validation: The Intel ExperienceKetan Paranjape. 1
- CMOS Testing at the End of the Roadmap: Challenges and OpportunitiesJaume Segura. 2
- An Hybrid Genetic Algorithm for Constrained Hardware-Software PartitioningPierre-André Mudry, Guillaume Zufferey, Gianluca Tempesti. 3-8
- Minimization of Large State Spaces using Symbolic Branching BisimulationRalf Wimmer, Marc Herbstritt, Bernd Becker. 9-14
- Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time AnalysisJochen Eisinger, Ilia Polian, Bernd Becker, Alexander Metzner, Stephan Thesing, Reinhard Wilhelm. 15-20
- A Low Power 2.5 Gbps 1: 32 Deserializer in SiGe BiCMOS TechnologyFélix Tobajas, Roberto Esper-Chaín, Raúl Regidor, O. Santana, Roberto Sarmiento. 21-26
- Six Subthreshold Full Adder Cells Characterized in 90 nm CMOS TechnologyKristian Granhaug, Snorre Aunet. 27-32
- A Low Complexity, High Speed, Regular and Flexible Reed Solomon Decoder for Wireless CommunicationAbid Rashid, Frank H. P. Fitzek, Ole Olsen, Morten Gade, Yannick Le Moullec. 33-38
- Comprehensive Design of a High Frequency PLL Synthesizer for ZigBee ApplicationAndrás Timár, Ábel Vámos, György Bognár. 39-43
- A Contextual Resources use: a Proof of Concept through the APACHES PlatformAlex Ngouanga, Gilles Sassatelli, Lionel Torres, André Borin Soares, Altamiro Amadeu Susin. 44-49
- LEON-2: General Purpose Processor for a Wireless EngineZoran Stamenkovic, C. Wolf, Günter Schoof, Jiri Gaisler. 50-53
- ReCoM: A New Reconfigurable Compute Fabric Architecture for Computation-Intensive ApplicationsLuca Sterpone, Massimo Violante. 54-58
- Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video EncoderAri Kulmala, Erno Salminen, Olli Lehtoranta, Timo D. Hämäläinen, Marko Hännikäinen. 59-64
- Parallel Memory Architecture for Arbitrary Stride AccessesEero Aho, Jarno Vanne, Timo D. Hämäläinen. 65-70
- Architecture Design for the Context Formatter in the H.264/AVC EncoderGrzegorz Pastuszak. 71-72
- Recognition of DRM Signal in Frequency Domain and Hardware DemandsLukas Ruckay. 73-74
- ISA Based Functional Test Generation with Application to Self-Test of RISC ProcessorsV. V. Belkin, S. G. Sharshunov. 75-76
- How to Improve a Set of Design Validation Data by Using Mutation-based TestYoussef Serrestou, Vincent Beroulle, Chantal Robach. 77-78
- Design and Verification Methodology for Reconfigurable Designs in Atmel FPSLICJiri Kadlec, Martin Danek. 79-80
- Die Attach Quality Testing by Fully Contact-less Measurement MethodGyörgy Bognár, Gyula Horváth, Zoltán Szucs, Vladimir Székely. 81-82
- A Flexible Technique for the Automatic Design of Approximate String Matching ArchitecturesTomás Martínek, Jan Korenek, Otto Fucík, Matej Lexa. 83-84
- Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational ModulesLukás Sekanina, Lukás Starecek, Zdenek Kotásek. 85-86
- Design of a Scalable Asynchronous Dataflow ProcessorHarri Lampinen, Pauli Perälä, Olli Vainio. 87-88
- Embedded Built-In-Test Detection Circuit for Radio Frequency Systems and CircuitsGuoyan Zhang, Ronan Farrell. 89-90
- Test Scheduling for SoC under Power ConstraintsJaroslav Skarvada. 91-93
- Self-refreshing Multiple Valued MemoryJohannes Goplen Lomsdalen, Renè Jensen, Yngvar Berg. 94-96
- Comparing Subtraction-Free and Traditional AMIJiri Bucek, Robert Lorencz. 97-99
- Dependability Computation for Fault Tolerant Reconfigurable Duplex SystemPavel Kubalík, Radek Dobias, Hana Kubatova. 100-102
- A New 6-bit Flash A/D Converter Using Novel Two-Step StructureShih-Chang Hsia, Wen-Ching Lee. 103-107
- A Novel Design Evaluation Concept Applied to Switched-Current Algorithmic A/D ConvertersOndrej Subrt, Pravoslav Martínek. 108-112
- Behavioral Modeling of WCDMA Transceiver with VHDL-AMS LanguageYves Joannon, Vincent Beroulle, Rami Khouri, Chantal Robach, Smail Tedjini, Jean-Louis Carbonéro. 113-118
- A Sinewave Analyzer for Mixed-Signal BIST Applications in a 0.35µm TechnologyManuel J. Barragan Asian, Diego Vázquez, Adoración Rueda. 119-124
- Lissajous Based Mixed-Signal Testing for N-Observable SignalsL. Balado, E. Lupon, L. García, Rosa Rodríguez-Montañés, Joan Figueras. 125-130
- PCA Data Preprocessing for Neural Network-based Detection of Parametric Defects in Analog ICP. Malosek, Viera Stopjaková. 131-135
- Productivity and Code Quality Improvement of Mixed-Signal Test Software by Applying Software Engineering MethodsStefan Vock, Ulrich Flogaus, Hans Martin von Staudt. 136-140
- On the Use of Information Redundancy When Designing Secure ChipsRégis Leveugle, V. Maingot. 141-142
- PE-ICE: Parallelized Encryption and Integrity Checking EngineReouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet. 143-144
- Normal Basis Multipliers of General Digit Width Applicable in Elliptic Curve CryptographyMartin Novotný, Jan Schmidt. 145-146
- Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design FlowMohamed Abbas, Makoto Ikeda, Kunihiro Asada. 147-148
- Run-Time Debugging and Monitoring of FPGA Circuits Using Embedded MicroprocessorAki Penttinen, Rafal Jastrzebski, Riku Pölläanen, Olli Pyrhönen. 149-150
- An Optimal Lower-Bound Algorithm for the High-Level Synthesis Scheduling ProblemGeguang Pu, Jifeng He, Zongyan Qiu. 151-152
- A System for Transforming an ANSI C Code with OpenMP Directives into a SystemC DescriptionPiotr Dziurzanski, W. Bielecki, Konrad Trifunovic, M. Kleszczonek. 153-154
- Low Level Bus Traffic Replay for the Test and Debugging of Time-Triggered Communication SystemsEric Armengaud. 155-156
- A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMsAlfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto. 157-158
- Hardware/Software Based Hierarchical Self Test for SoCsRené Kothe, Christian Galke, S. Schultke, H. Froeschke, S. Gaede, Heinrich Theodor Vierhaus. 159-160
- Power-Constrained, Sessionless SoC Test Scheduling Based on Exploration of I-Schedule State-SpaceJosef Strnadel. 161-162
- Design-for-Test of Asynchronous Networks-on-ChipXuan-Tu Tran, Vincent Beroulle, Jean Durupt, Chantal Robach, François Bertrand. 163-167
- Can Clock Faults be Detected Through Functional Test?Cecilia Metra, Daniele Rossi, Martin Omaña, José Manuel Cazeaux, T. M. Mak. 168-173
- A Modified Debugging Infrastructure to Assist Real Time Fault Injection CampaignsAndré V. Fidalgo, Gustavo R. Alves, José M. Ferreira. 174-179
- Low-Cost Concurrent Error Detection for FSMs Implemented Using Embedded Memory Blocks of FPGAsAndrzej Krasniewski. 180-185
- Fault-Tolerant 2-D Mesh Network-on-Chip for Multi-Processor System-on-ChipHeikki Kariniemi, Jari Nurmi. 186-191
- A Flexible SoPC-based Fault Injection EnvironmentPierre Vanhauwaert, Régis Leveugle, Philippe Roche. 192-197
- Generation and Propagation of Single Event Transients in CMOS CircuitsGilson I. Wirth, Michele G. Vieira, Egas Henes Neto, Fernanda Gusmão de Lima Kastensmidt. 198-203
- Concurrent Testing of Digital Circuits for Advanced Fault ModelsS. Biswas, S. Mukhopadhyay, P. Patra, D. Sarkar. 204-209
- Embedded Self Repair by Transistor and Gate Level ReconfigurationRené Kothe, Heinrich Theodor Vierhaus, Torsten Coym, Wolfgang Vermeiren, Bernd Straube. 210-215
- Probabilistic Testability Analysis and DFT Methods at RTLJosé M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, João C. Teixeira. 216-217
- An Extension of Transient Fault Emulation Techniques to Circuits with Embedded MemoriesMario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena-Arrontes. 218-219
- Optimal Memory Address Seeds for Pattern Sensitive Faults DetectionS. V. Yarmolik, B. Sokol. 220-221
- Evolutionary Design of OAB and AAB Communication Schedules for Networking Systems on ChipsJirí Jaros, Václav Dvorák. 222-223
- Collective Communication AAB for Regular and Irregular Topology Based on Prediction of ConflictsMilos Ohlídal, Josef Schwarz. 224-225
- A Switch Supporting Circuit and Packet Switching for On-Chip NetworksHsin-Chou Chi, Chia-Ming Wu, Sung-Tze Wu. 226-227
- FPGA Implementation of a Fast MDCT AlgorithmMartin Simlastík, Peter Malík, Tomás Pikula, Marcel Baláz. 228-229
- Detection, Localisation and Identification of Interconnection Faults Using MISR CompactorTomasz Garbolino, Michal Kopec, Krzysztof Gucwa, Andrzej Hlawiczka. 230-231
- Test Considerations about the Structured ASIC ParadigmPaolo Bernardi, Michelangelo Grosso. 232-233
- A Leakage-based Random Bit Generator with On-line Fault DetectionMarco Bucci, Raimondo Luzzi. 234-235
- New Current Monitor Using Auto Zero Voltage Comparator for IDD Testing of Mixed-signal CircuitsVladislav Nagy, Viera Stopjaková. 236-237
- A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel ProgrammingZbysek Gajda. 238-240
- SOC Diagnostic Design Using RESPIN ArchitectureZbynek Mader, Michal Jarkovský. 241-243
- Dynamic Decimal Adder Circuit Design by using the Carry LookaheadYounggap You, Yong-Dae Kim, Jong Hwa Choi. 244-246
- Multiple Valued CounterJohannes Goplen Lomsdalen, Renè Jensen, Yngvar Berg. 247-249
- HW Implementation of the Backtrace Algorithm with Conflict-Driven Dynamic ReconfigurationMartin Stáva, Ondrej Novák. 250-252
- Sensor Powering with Integrated MOS Compatible Solar Cell ArrayGergely Perlaky, Gábor Mezösi, Imre Zolomy. 253-255
- March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge CircuitLuigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian. 256-261
- Minimal March-Based Fault Location Algorithm with Partial Diagnosis for all Static Faults in Random Access MemoriesGurgen Harutunyan, Valery A. Vardanian, Yervant Zorian. 262-267
- Multiple-Vector Column-Matching BIST Design MethodPetr Fiser, Hana Kubatova. 268-273
- FPGA-based Fault SimulatorLeos Kafka, Ondrej Novák. 274-278
- Functional-Oriented BIST of Sequential Circuits Aiming at Dynamic Faults CoverageF. Guerreiro, Jorge Semião, A. Pierce, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. 279-284
- FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic PropertiesTomas Pecenka, Zdenek Kotásek, Lukás Sekanina. 285-289