Abstract is missing.
- Enhancing sequential depth computation with a branch-and-bound algorithmChia-Chih Yen, Jing-Yang Jou. 3-8 [doi]
- Reference model based RTL verification: an integrated approachWilliam N. N. Hung, Naren Narasimhan. 9-13 [doi]
- Dynamic guiding of bounded property checkingPrakash Mohan Peranandam, Roland J. Weiss, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel. 15-18 [doi]
- Towards an efficient assertion based verification of SystemC designsAli Habibi, Sofiène Tahar. 19-22 [doi]
- Instruction level test methodology for CPU core software-based self-testingSaeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi. 25-29 [doi]
- Simplifying design and verification for structural hazards and datapaths in pipelined circuitsJason T. Higgins, Mark Aagaard. 31-36 [doi]
- ATPG based functional test for data paths: application to a floating point unitIsmet Bayraktaroglu, Manuel d'Abreu. 37-40 [doi]
- Formal verification of pipelined processors with load-value predictionMiroslav N. Velev. 41-46 [doi]
- On using a 2-domain partitioned OBDD data structure in verificationTao Feng, Li-C. Wang, Kwang-Ting Cheng, Andy Lin. 49-54 [doi]
- Variable ordering for taylor expansion diagramsDaniel Gomez-Prado, Qian Ren, Serkan Askar, Maciej J. Ciesielski, Emmanuel Boutillon. 55-59 [doi]
- MODD for CF: a representation for fast evaluation of multiple-output functionsT. L. Rajaprabhu, Ashutosh Kumar Singh, Abusaleh M. Jabir, Dhiraj K. Pradhan. 61-66 [doi]
- Functional verification based on the EFSM modelFranco Fummi, Cristina Marconcini, Graziano Pravadelli. 69-74 [doi]
- Enhancing the efficiency of Bayesian network based coverage directed test generationMarkus Braun, Shai Fine, Avi Ziv. 75-80 [doi]
- Mutation-based validation of high-level microprocessor implementationsJorge Campos, Hussain Al-Asaad. 81-86 [doi]
- Effects of property ordering in an incremental formal modeling methodologySyed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla. 89-94 [doi]
- Efficient test-based model generation for legacy reactive systemsTiziana Margaria, Oliver Niese, Harald Raffelt, Bernhard Steffen. 95-100 [doi]
- Model validation for mapping specification behaviors to processing elementsSamar Abdi, Daniel Gajski. 101-106 [doi]
- Test quality for high level structural testAhmad A. Al-Yamani, Edward J. McCluskey. 109-114 [doi]
- On code coverage measurement for Verilog-AYuan-Bin Sha, Mu-Shun Matt Lee, Chien-Nan Jimmy Liu. 115-120 [doi]
- On identifying functionally untestable transition faultsXiao Liu, Michael S. Hsiao. 121-126 [doi]
- CNF formula simplification using implication reasoningRajat Arora, Michael S. Hsiao. 129-134 [doi]
- Dynamic analysis of constraint-variable dependencies to guide SAT diagnosisVijay Durairaj, Priyank Kalla. 135-140 [doi]
- Exploiting hypergraph partitioning for efficient Boolean satisfiabilityVijay Durairaj, Priyank Kalla. 141-146 [doi]
- An event-based network-on-chip monitoring serviceCalin Ciordas, Twan Basten, Andrei Radulescu, Kees Goossens, Jef L. van Meerbergen. 149-154 [doi]
- Assertion-based power/performance analysis of network processor architecturesJia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang 0002, Felice Balarin. 155-160 [doi]
- Validation of the dependability of CAN-based networked systemsFulvio Corno, Julio Pérez Acle, Mattia Ramasso, Matteo Sonza Reorda, Massimo Violante. 161-164 [doi]
- High level hardware validation using hierarchical message sequence chartsPraveen K. Murthy, Sreeranga P. Rajan, Koichiro Takayama. 167-172 [doi]
- Analysis of the influence of processor hidden registers on the accuracy of fault injection techniquesDaniel Gil, Joaquin Gracia, Juan Carlos Baraza, Pedro J. Gil. 173-178 [doi]
- On equivalence checking between behavioral and RTL descriptionsMasahiro Fujita. 179-184 [doi]
- Panel: Driving the intelligent testbanch: are we there yet?Harry Foster. 188 [doi]
- Panel: What happened to the intelligent test bench?Gary Smith. 189 [doi]