Abstract is missing.
- A compact multi-input thermoelectric energy harvesting system with 58.5% power conversion efficiency and 32.4-mW output power capabilityChia-Lun Chang, Tai-Cheng Lee. 1-4 [doi]
- A maximum power point tracking and voltage regulated dual-chip system for single-cell photovoltaic energy harvestingWen-Yaw Chung, Pei-Shan Yu, Angelito A. Silverio. 5-8 [doi]
- Modeling and implementation of high-gain switched-inductor switched-capacitor converterYuen-Haw Chang, Yu-Jhang Chen. 9-12 [doi]
- A three-topology based, wide input range switched-capacitor DC-DC converter with low-ripple and enhanced load line regulationsHendika Fatkhi Nurhuda, Yongkui Yang, Wang Ling Goh. 13-16 [doi]
- Triple boundary multiphase with predictive interleaving technique for switched capacitor DC-DC converter regulationZhekai Xiao, Chiang Liang Kok, Liter Siek. 17-20 [doi]
- Investigating measurement methods for high-resolution electromagnetic field side-channel analysisRobert Specht, Johann Heyszl, Georg Sigl. 21-24 [doi]
- Side-channel analysis of a high-throughput AES peripheral with countermeasuresBenedikt Heinz, Johann Heyszl, Frederic Stumpf. 25-29 [doi]
- Zero collision attack and its countermeasures on Residue Number System multipliersMarc Stöttinger, Gavin Xiaoxu Yao, Ray C. C. Cheung. 30-33 [doi]
- Constructive side-channel analysis for secure hardware designAlexander Herrmann, Marc Stöttinger. 34-37 [doi]
- Overview of machine learning based side-channel analysis methodsDirmanto Jap, Jakub Breier. 38-41 [doi]
- A low-power direct IQ upconversion technique based on duty-cycled multi-phase sub-harmonic passive mixers for UWB transmittersAmin Ojani, Behzad Mesgarzadeh, Atila Alvandpour. 42-45 [doi]
- Timing challenges in high-speed interleaved ΔΣ DACsAmeya Bhide, Atila Alvandpour. 46-49 [doi]
- mm-Wave pulse-generation circuits in 65nm CMOSMarkus Tormanen. 50-53 [doi]
- A 65 nm CMOS varactorless mm-wave VCOTherese Forsberg, Henrik Sjöland, Markus Törmänen. 54-57 [doi]
- A 28 GHz SiGe QVCO with an I/Q phase error detector for an 81-86 GHz E-band transceiverTobias Tired, Henrik Sjöland, Carl Bryant, Markus Törmänen. 58-61 [doi]
- QED post-silicon validation and debug: Invited abstractDavid Lin, Subhasish Mitra. 62 [doi]
- Energy-efficient computing with heterogeneous multi-coresTulika Mitra. 63-66 [doi]
- A user's reflections on the art of high level synthesisYu Pan, Santhosh Kumar Pilakkat, Kay-Chuan Benny Tan, Wai-Meng Mok. 67-70 [doi]
- New solutions for system-level and high-level synthesis (Invited paper)Wei Zuo, Hongbin Zheng, Swathi T. Gurumani, Kyle Rupnow, Deming Chen. 71-74 [doi]
- Digital compensation method for the path delay mismatches in GRO-TDCPyoungwon Park, Dipankar Nag, Dan Lei Yan, Muthukumaraswamy Annamalai Arasu. 75-78 [doi]
- Digital phase locked loop (DPLL) with offset dithered bang-bang phase detector (BBPD) for bandwidth controlYounghoon Kim, Min-Ki Jeon, Changsik Yoo. 79-82 [doi]
- A 14-bit 100MS/s pipelined A/D converter with 2b interstage redundancyKun Ao, Yajuan He, Liang Li, Yuxin Wang, Qiang Li. 83-86 [doi]
- Design of a 4 GS/s radix-1.75 single channel pipeline ADC in 28 nm CMOS technology with foreground calibrationFelix Lang, Markus Grozing, Manfred Berroth. 87-90 [doi]
- A high efficiency CMOS rectifier with ON-OFF response compensation for wireless power transfer in biomedical applicationsQiang Li, Jing Wang, Yasuaki Inoue. 91-94 [doi]
- Statistical power optimization of deep-submicron digital CMOS circuits based on structured perceptronAmir Zjajo, Nick van der Meijs, Rene van Leuken. 95-98 [doi]
- Vt-conscious repeater insertion in power-managed VLSIHouman Zarrabi, Asim J. Al-Khalili, Yvon Savaria. 99-102 [doi]
- An improved scan cell ordering method using the scan cells with complementary outputsMengyang Li, Aijiao Cui, Tingting Yu. 103-106 [doi]
- Ray-casting algorithm and its considerations for parallel processing optimization techniques for parallel ray-casting algorithmHanjoo Cho, Young-Hwan Kim. 107-110 [doi]
- A hierarchical switch matrix and interconnect resources test in Virtex-5 FPGAA. W. Ruan, W. Tian, B. Ni, K. Wu. 111-114 [doi]
- Ultra-low-power biomedical circuit design and optimization: Catching the don't caresXin Li 0001, Ronald Shawn Blanton, Pulkit Grover, Donald E. Thomas. 115-118 [doi]
- SLIC: Statistical learning in chipRonald D. Blanton, Xin Li, Ken Mai, Diana Marculescu, Radu Marculescu, Jeyanandh Paramesh, Jeff G. Schneider, Donald E. Thomas. 119-123 [doi]
- Neuromorphic hardware acceleration enabled by emerging technologies (Invited paper)Hai Li, Xiaoxiao Liu, Mengjie Mao, Yiran Chen, Qing Wu, Mark Bamell. 124-127 [doi]
- Architectural exploration for on-chip, online learning in spiking neural networksSubhrajit Roy, Sougata Kumar Kar, Arindam Basu. 128-131 [doi]
- An improved SPICE model of phase-change memory (PCM) for peripheral circuits simulation and designYiqun Wei, Xinnan Lin. 132-135 [doi]
- Advanced performance metrics for Physical Unclonable FunctionsMichael Pehl, Akshara Ranjit Punnakkal, Matthias Hiller, Helmut Graeb. 136-139 [doi]
- Reconfigurable PUFs for FPGA-based SoCsStefan Gehrer, Georg Sigl. 140-143 [doi]
- Lightweight cryptography for constrained devicesCesare Alippi, Andrey Bogdanov, Francesco Regazzoni. 144-147 [doi]
- Statistic-based security analysis of ring oscillator PUFsFlorian Wilde, Matthias Hiller, Michael Pehl. 148-151 [doi]
- A survey of the state-of-the-art fault attacksJakub Breier, Dirmanto Jap. 152-155 [doi]
- A fully integrated 166-GHz frequency synthesizer in 0.13-μm SiGe BiCMOS for D-band applicationsJin He, Yong-Zhong Xiong, Jian Kang Li, Debin Hou, Sanming Hu, Dan Lei Yan, Muthukumaraswamy Annamalai Arasu, Yue-Ping Zhang. 156-159 [doi]
- A 2.5-GHz band low-voltage high efficiency class-E power amplifier IC with body effectTaufiq Alif Kurniawan, Xin Yang, Xiao Xu, Zheng Sun, Toshihiko Yoshimasu. 160-163 [doi]
- A 20.5GHz wide-band programmable divide-by-N frequency dividerTing Guo, Zhiqun Li, Qin Li, Zhigong Wang. 164-167 [doi]
- A dual-band VCO using inductor splitting for automotive radar system at W-bandJongsuk Lee, Yong Moon, Taewon Ahn. 168-171 [doi]
- Challenging the limits of FFT performance on FPGAs (Invited paper)Mario Garrido, Miguel Acevedo, Andreas Ehliar, Oscar Gustafsson. 172-175 [doi]
- Subquadratic space complexity digit-serial multiplier over binary extension fields using Toom-Cook algorithmChiou-Yng Lee, Pramod Kumar Meher, Wen-Yo Lee. 176-179 [doi]
- A new memoryless and low-latency FFT rotator architectureShen-Jui Huang, Sau-Gee Chen. 180-183 [doi]
- Cost-efficiency FFT using hardware-reduction and dynamic current scaling approachesYing-Liang Chen, Terng-Yin Hsu. 184-187 [doi]
- Fast binary to BCD converters for decimal communications using new recoding circuitsTso-Bing Juang, Yu-Ming Chiu. 188-191 [doi]
- The role of auditory feedback in speech production: Implications for speech perception in the hearing impairedDongying Liang, Yan Xiao, Yongqiang Feng, Yonghong Yan 0002. 192-195 [doi]
- An efficient spectral subtraction-based strategy for suppressing reverberation in cochlear implant devicesKostas Kokkinakis, Yi Hu, Dongying Liang. 196-199 [doi]
- Perceptual contribution of vowels and consonants to sentence intelligibility by cochlear implant usersQudsia Tahmina, Fei Chen, Yi Hu. 200-203 [doi]
- Effect of adaptive envelope compression in simulated electric hearing in reverberationYing-Hui Lai, Fei Chen, Yu Tsao. 204-207 [doi]
- Intra- and inter-chip voltage droop analysis using a power delivery grid modelWing Oi Siu, Terrence Mak. 208-211 [doi]
- Time-efficient computation of digit serial Montgomery multiplicationWangchen Dai, Huapeng Wu, Ray C. C. Cheung. 212-215 [doi]
- The Internet of Things: An overview and new perspectives in systems designJun Wei Chuah. 216-219 [doi]
- A heterogeneous platform with GPU and FPGA for power efficient high performance computingQiang Wu, Yajun Ha, Akash Kumar 0001, Shaobo Luo, Ang Li, Shihab Mohamed. 220-223 [doi]
- Thermal-aware task scheduling for 3D-network-on-chip: A Bottom-to-Top schemeYingnan Cui, Wei Zhang, Vivek Chaturvedi, Weichen Liu, Bingsheng He. 224-227 [doi]
- A low-distortion R-active-C lowpass filter for linear sensor applicationsD. Wang, P. K. Chan. 228-231 [doi]
- A versatile three-stage operational amplifier with Second-stage Bypass CompensationUday Dasgupta, G. T. Ong, J. M. Cao, S.-L. Chew. 232-235 [doi]
- A primary side feedback control for flyback LED driver with no output voltage feedback resistorsZhelu Li, Yahui Leng, Xufeng Wu, Jianxiong Xi, Lenian He. 236-239 [doi]
- An SOI-CMOS low noise chopper amplifier for high temperature applicationsYejin Chen, Goh Wang-Ling, Jun Yu, Muthukumaraswamy Annamalai Arasu. 240-243 [doi]
- A 66dB continuous gain adjusting CMOS AGC amplifier with both feedforward and feedback loopChunfeng Bai, Jianhui Wu. 244-247 [doi]
- ASIC implementation of the cross frequency coupling algorithm for EEG signal processingPhilip Davis, Charles D. Creusere, Wei Tang Klipsh. 248-251 [doi]
- A second-generation noise-immune motion detection image sensor for moving object tracking applicationXiangyu Zhang, Shoushun Chen. 252-255 [doi]
- The design and verification of a novel LDPC decoder with high-efficiencyDan Yang, Guoyi Yu, Xuecheng Zou, Yelei Deng, Jianfu Zhong. 256-259 [doi]
- A highly-integrated wireless configuration circuit for FPGA chipTongqiang Gao, Xiaodong Xu, Hongfeng Zhang, Haigang Yang. 260-263 [doi]
- Power distribution network design for high-speed automotive graphical processing moduleLin Biao Wang, Kye Yak See. 264-267 [doi]
- Energy efficient spiking neural network design with RRAM devicesTianqi Tang, Rong Luo, Boxun Li, Hai Li, Yu Wang, Huazhong Yang. 268-271 [doi]
- VLSI architecture of a high-performance neural spiking activity simulator based on generalized Volterra kernelWill X. Y. Li, Yao Xin, Dong Song, Theodore W. Berger, Ray C. C. Cheung. 272-275 [doi]
- A real-time silicon cerebellum spiking neural model based on FPGAJunwen Luo, Graeme Coapes, Patrick Degenaar, Tadashi Yamazaki, Terrence S. T. Mak, Chung Tin. 276-279 [doi]
- Trade-offs between the sensitivity and the speed of the FPGA-based sequence alignerPeng Chen, Chao Wang, Xi Li, Xuehai Zhou, Aili Wang, Ray C. C. Cheung. 280-283 [doi]
- Hierarchical air quality monitoring system designYangyang Ma, Shengqi Yang, Zhangqin Huang, Yibin Hou, Leqiang Cui, Dongfang Yang. 284-287 [doi]
- A 330 GHz frequency modulator using 0.13-μm SiGe HBTsYihu Li, Yong-Zhong Xiong, Goh Wang-Ling. 288-291 [doi]
- An overview of new design techniques for high performance CMOS millimeter-wave circuitsShunli Ma, Junyan Ren, Hao Yu. 292-295 [doi]
- A fully integrated 166-GHz frequency synthesizer in 0.13-μm SiGe BiCMOS for D-band applicationsJin He, Yong-Zhong Xiong, Jiankang Li, Debin Hou, Sanming Hu, Dan Lei Yan, Muthukumaraswamy Annamalai Arasu, Yue-Ping Zhang. 296-299 [doi]
- A 340 GHz fully integrated transmitter for high-speed communicationsXiaodong Deng, Yihu Li, Jiankang Li, Wen Wu, Yong-Zhong Xiong. 300-303 [doi]
- A compact Ka-band SPDT switch with high isolationChao Liu, Qiang Li, Yong-Zhong Xiong. 304-307 [doi]
- A 150-GHz push-push VCO in 0.13-μm SiGe BiCMOSJiang Luo, Jin He, Hao Wang, Sheng Chang, Qijun Huang, Yong-Zhong Xiong. 308-311 [doi]
- High-speed and low-leakage FinFET SRAM cell with enhanced read and write voltage marginsShairfe Muhammad Salahuddin, Volkan Kursun. 312-315 [doi]
- Novel STT-MRAM-based last level caches for high performance processors using normally-off architecturesShinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe. 316-319 [doi]
- A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operationWeng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, Ne Kyaw Zwa Lwin. 320-323 [doi]
- Design of threshold dominant delay Physical Unclonable Functions in 65nm CMOSYuejun Zhang, Pengjun Wang, Jianrui Li, Gang Li. 324-327 [doi]
- MTCMOS low-power design technique (LPDT) for low-voltage pipelined microprocessor circuitsC. B. Hsu, J. B. Kuo. 328-331 [doi]
- Case study: Effectiveness of dynamic frequency scaling on server workloadHitoshi Oi. 332-335 [doi]
- Scaling Java Virtual Machine on a many-core systemKarthik Ganesan, Yao-Min Chen, Xiaochen Pan. 336-339 [doi]
- A hybrid mapreduce model for prologJoana Côrte-Real, Inês de Castro Dutra, Ricardo Rocha. 340-343 [doi]
- Acceleration of Naive-Bayes algorithm on multicore processor for massive text classificationLijun Zhou, Zhiyi Yu, Jie Lin, Shikai Zhu, Weijing Shi, Haijie Zhou, Kunpeng Song, Xiaoyang Zeng. 344-347 [doi]
- Differences of energetic consumption between Java and JNI Android appsRicardo Isidro Ramirez, Erika Hernandez Rubio, Amilcar Meneses Viveros, Irene Monserrat Torres Hernandez. 348-351 [doi]
- Performance and cost analysis of NoC-inspired virtual topologies for digital microfluidic biochipsDaniel T. Grissom, Jeffrey McDaniel, Philip Brisk. 352-355 [doi]
- Online synthesis for operation execution time variability on digital microfluidic biochipsMirela Alistar, Paul Pop. 356-359 [doi]
- Recent trends in chip-level design automation for digital microfluidic biochipsSudip Roy 0001, Chi-Ruo Wu, Tsung-Yi Ho. 360-363 [doi]
- Sample preparation for droplet-based microfluidicsJuinn-Dar Huang, Chia-Hung Liu. 364-367 [doi]
- Mask-based non-maximal suppression with iterative pruning for low-complexity corner detectionNirmala Ramakrishnan, Meiqing Wu, Siew Kei Lam, Thambipillai Srikanthan. 368-371 [doi]
- Vision-based pedestrian tracking system using color and motion cueMeiqing Wu, Siew Kei Lam, Thambipillai Srikanthan, Tushar Shah. 372-375 [doi]
- Reducing computational complexity for face detectionSupriya Sathyanarayana, Ravi Kumar Satzoda, Suchitra Sathyanarayana, Srikanthan Thambipillai. 376-379 [doi]
- Development of driver assistance systems using virtual hardware-in-the-loopPhilipp Wehner, Fynn Schwiegelshohn, Diana Göhringer, Michael Hübner. 380-383 [doi]
- A pipelined architecture for motion tracking on a multicore environmentN. Sudha, K. Sridharan, Dan Wilkinson. 384-387 [doi]
- A 0.3-V, 37.5-nW 1.5∼6.5-pF-input-range supply voltage tolerant capacitive sensor readoutSuyan Fan, Man Kay Law, Pui-In Mak, Rui Paulo Martins. 388-391 [doi]
- CMOS image sensor based physical unclonable function for smart phone security applicationsYuan Cao, Siarhei S. Zalivaka, Le Zhang, Chip-Hong Chang, Shoushun Chen. 392-395 [doi]
- ASIC front-end for sensing MEMS-mirror positionLeo John Chemmanda, Colin Chue Jianrong, Ravinder Pal Singh, Yalon Roterman. 396-399 [doi]
- High accuracy time-mode duty-cycle-modulation-based temperature sensor for energy efficient system applicationsDi Zhu, Jiacheng Wang, Liter Siek, Chiang Liang Kok, Lei Qiu, Yuanjin Zheng. 400-403 [doi]
- High performance ΣΔ closed loop accelerometerDipankar Nag, Kevin Chai Tshun Chuan. 404-407 [doi]
- High accuracy remote temperature sensor based on BJT devices in 0.13-μm CMOSSeong-Jin Kim, Simon Sheung Yan Ng, David Wee, Yoon Hwee Leow, Fan-Yung Ma, Sie Boo Chiang. 408-411 [doi]
- Parasitic BJT versus DIBL: Floating-body-related subthreshold characteristics of SOI NMOS deviceD. H. Lung, S. K. Hu, J. B. Kuo, D. Chen, Y. J. Chen. 412-415 [doi]
- Effect of AC stress on oxide TDDB and trapped charge in interface statesB. Rebuffat, Pascal Masson, Jean-Luc Ogier, M. Mantelli, Romain Laffont. 416-419 [doi]
- The increase sensitivity of PNP-magnetotransistor in CMOS technologyChana Leepattarapongpan, Toempong Phetchakul, Puttapon Pengpad, Arckom Srihapat, Wutthinan Jeamsaksiri, Ekalak Chaowicharat, Charndet Hruanun, Amporn Poyai. 420-423 [doi]
- Analysis and modelling on CMOS spiral inductor with impact of metal dummy fillsYong Wang, Bo Chen, Supeng Liu, Liheng Lou, Kai Tang, Ying Zhang, Yuanjin Zheng. 424-427 [doi]
- A semi-analytical extraction method for transformer modelBo Chen, Liheng Lou, Supeng Liu, Kai Tang, Yong Wang, Jianjun Gao, Yuanjin Zheng. 428-431 [doi]
- n + 3}Pedro Miguens Matutino, Ricardo Chaves, Leonel Sousa. 432-435 [doi]
- Twenty years of research on RNS for DSP: Lessons learned and future perspectivesPietro Albicocco, Gian-Carlo Cardarilli, Alberto Nannarelli, Marco Re. 436-439 [doi]
- Babaï round-off CVP method in RNS: Application to lattice based cryptographic protocolsJean-Claude Bajard, Julien Eynard, Nabil Merkiche, Thomas Plantard. 440-443 [doi]
- Rethinking reverse converter design: From algorithms to hardware componentsAmir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Seyed Mostafa Mirhosseini, Mehdi Hosseinzadeh. 444-447 [doi]
- A low-cost architecture for DWT filter banks in RNS applicationsYinan Kong, Azadeh Safari, Cheeckottu Vayalil Niras. 448-451 [doi]
- ECRT: An extension of CRT based on weight pre-assignmentShang Ma, Chen-Hao Wang, JianHao Hu, Hongyan Chen. 452-455 [doi]
- Diagnosis-aware system design for automotive E/E architecturesPeter Waszecki, Florian Sagstetter, Martin Lukasiewycz, Samarjit Chakraborty. 456-459 [doi]
- System C-based multi-level error injection for the evaluation of fault-tolerant systemsDaniel Mueller-Gritschneder, Petra R. Maier, Marc Greim, Ulf Schlichtmann. 460-463 [doi]
- Fault-tolerant embedded control systems for unreliable hardwareDip Goswami, Daniel Mueller-Gritschneder, Twan Basten, Ulf Schlichtmann, Samarjit Chakraborty. 464-467 [doi]
- System simulation and optimization using reconfigurable hardwareMartin Lukasiewycz, Shanker Shreejith, Suhaib A. Fahmy. 468-471 [doi]
- Apps-usage driven energy management for multicore mobile computing systemsHou Zhao Qi Rex, Jong Ching Chuen, Andreas Herkersdorf. 472-475 [doi]
- Low noise linear and wideband transconductance amplifier design for current-mode frontendQuoc-Tai Duong, Atila Alvandpour. 476-479 [doi]
- A self-oscillating class D audio amplifier with dual voltage and current feedbackSalma Nashit, Victor Adrian, Cui Keer, Quoc-An Mai, Bah-Hwee Gwee, Joseph S. Chang. 480-483 [doi]
- Transducer driver with active bootstrap switchJun Yu, Muthukumaraswamy Annamalai Arasu. 484-487 [doi]
- Design of an output stage for high switching frequency DC-DC convertersTian-Shun Ng, Yin Sun, Victor Adrian, Bah-Hwee Gwee, Joseph S. Chang. 488-491 [doi]
- A digital calibration technique for multi-bit-per-stage pipelined ADCYajuan He, Song Wang, Qi Ling, Qiang Li. 492-495 [doi]
- A small area 10-bit linear gamma DAC with voltage adder for large-sized active matrix flat panel displaysJae-Yoon Bae, Hyeon-Cheon Seol, Young-Cheon Kwon, Seong-Kwan Hong, Oh-Kyong Kwon, Seong-Hwan Hwang, Seung-Tae Kim. 496-499 [doi]
- A 40nm/65nm process adaptive low jitter phase-locked loopHengzhou Yuan, Yang Guo, Zhuo Ma. 500-503 [doi]
- A versatile biopotential acquisition analog front end IC with effective DC offset and ripple rejectionSeunghyun Im, Changho Seok, Hyunho Kim, Haryong Song, Hyoungho Ko, Dong-Il Dan Cho. 504-507 [doi]
- n + 1}Hillary Siewobr, Kazeem Alagbe Gbolagade, Sorin Cotofana. 508-511 [doi]
- FPGA-based quantum circuit emulation: A case study on Quantum Fourier transformYee Hui Lee, Mohamed Khalil Hani, Muhammad N. Marsono. 512-515 [doi]
- Low-power multi-function multi-mode baseband design for low data rate applicationsBin Zhao, Hongbao Zhang, LayKeng Lim, Xin Liu, M. Kumarasamy Raja. 516-519 [doi]
- Design and characterization of radiation-tolerant CMOS 4T Active Pixel SensorsXinyuan Qian, Hang Yu, Shoushun Chen, Kay-Soon Low. 520-523 [doi]
- A more accurate circuit model for CMOS Hall cross with non-linear resistors and JFETsFei Lyu, Zhenduo Zhu, Zhenfei Lu, Li Li 0003, Jin Sha, Hongbing Pan, Yutong Bi. 524-527 [doi]
- An amperometric sensor readout circuit for multiple electrochemical sensor cellsWen-Yaw Chung, Angelito A. Silverio, Vincent F. S. Tsai. 528-531 [doi]
- A novel amperometric sensor readout based on charge measurement by current integrationWen-Yaw Chung, Angelito A. Silverio, Ming-Ying Zhou, Vincent F. S. Tsai. 532-535 [doi]
- DC - 15 GHz CMOS SP8T switches using defected ground structure low pass filterAnak Agung Alit Apriyana, Yue-Ping Zhang. 536-539 [doi]
- Modeling of two port center-tapped to ground and three port scalable symmetrical inductorWei Yi Lim, M. Annamalai Arasu, M. Kumarasamy Raja. 540-543 [doi]
- A +33dBm 1.9 GHz linear CMOS power amplifier with MOS-level linearizersZhi-xiong Ren, Kefeng Zhang, Lan-qi Liu, Cong Li, Xiaofei Chen, Dongsheng Liu, Zhenglin Liu, Xuecheng Zou. 544-547 [doi]
- A broadband CMOS LC voltage-controlled oscillator for FMCW synthesizerLiheng Lou, Supeng Liu, Bo Chen, Kai Tang, Yong Wang, Yuanjin Zheng. 548-551 [doi]
- A low power injection-locked divider for body sensor networkDawei Li, Dongsheng Liu, Xuecheng Zou, Zilong Liu, Lun Li. 552-555 [doi]
- A 400MHz low power fractional-N synthesizer with GFSK/GMSK modulation in 0.13μm CMOSDan Lei Yan, Zhao Bin, Atshushi Tamura, M. Kumarasamy Raja. 556-559 [doi]
- Deep packet inspection in residential gateways and routers: Issues and challengesSubramanian Shiva Shankar, Pinxing Lin, Andreas Herkersdorf. 560-563 [doi]
- Development of a variable frequency impedance measuring systemAngelina Silverio, Angelito Silverio, Joseph Demferlee Tatel. 564-567 [doi]
- Internet of Things: Trends, challenges and applicationsKiat Seng Yeo, Mojy Curtis Chian, Tony Chon Wee Ng, Anh-Tuan Do. 568-571 [doi]
- Zone classification for low-power active RFID tagsFelis Dwiyasa, Meng-Hiot Lim. 572-575 [doi]
- A ramping method combined with the damped PTA algorithm to find the DC operating points for nonlinear circuitsZhou Jin, Xiao Wu, Yasuaki Inoue, Dan Niu. 576-579 [doi]
- Design of a 4-bit programmable delay with TDC-based BIST for use in serial data linksTaha Mehrabi, Kaamran Raahemifar, Vadim Geurkov. 580-583 [doi]
- Automatic adjustment system for optical interconnection transmitter using improved particle swarm optimizationKenichi Ohhata, Hiroki Nakahara, Takuya Inoue, Toru Yazaki, Norio Chujo, Takuma Nishimoto. 584-587 [doi]
- The limitation for the growth of step of DPTA methodXiao Wu, Zhou Jin, Dan Niu, Yasuaki Inoue. 588-591 [doi]
- A bitstream readback based FPGA test and diagnosis systemT. Du A. W. Ruan, P. Li B. R. Jie. 592-595 [doi]
- A modular design of elliptic-curve point multiplication for resource constrained devicesWei Wei, Li Zhang, Chip-Hong Chang. 596-599 [doi]
- Conversions between RNS and mixed-radix numbers using signed-digit arithmeticShugang Wei. 600-603 [doi]
- NuDE 2.0: A model-based software development environment for the PLC & FPGA based digital systems in nuclear power plantsJunbeom Yoo, Eui-Sub Kim, Dong-Ah Lee, Jong-Gyun Choi, Young-Jun Lee, Jang-Soo Lee. 604-607 [doi]
- Obfuscation and watermarking of FPGA designs based on constant value generatorsVladimir V. Sergeichik, Alexander A. Ivaniuk, Chip-Hong Chang. 608-611 [doi]