Table of Contents

• Wireless beyond the third generation wireless beyond the third generation: facing the energy challengeJan M. Rabaey. 1-3 [doi]
• Micro-operation cache: a power aware frontend for the variable instruction length ISABaruch Solomon, Avi Mendelson, Doron Orenstein, Yoav Almog, Ronny Ronen. 4-9 [doi]
• L1 data cache decomposition for energy efficiencyMichael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas. 10-15 [doi]
• Instruction flow-based front-end throttling for power-aware high-performance processorsAmirali Baniasadi, Andreas Moshovos. 16-21 [doi]
• Energy reduction in queues and stacks by adaptive bitwidth compressionVasily G. Moshnyaga. 22-27 [doi]
• Energy priority scheduling for variable voltage processorsJohan A. Pouwelse, Koen Langendoen, Henk J. Sips. 28-33 [doi]
• Dynamic voltage scheduling technique for low-power multimedia applications using buffersChaeseok Im, Huiseok Kim, Soonhoi Ha. 34-39 [doi]
• Power-aware modulo scheduling for high-performance VLIW processorsHan-Saem Yun, Jihong Kim. 40-45 [doi]
• Hard real-time scheduling for low-energy using stochastic data and DVS processorsFlavius Gruian. 46-51 [doi]
• Analysis and design of low-energy flip-flopsDejan Markovic, Borivoje Nikolic, Robert W. Brodersen. 52-55 [doi]
• Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variationHoang Q. Dao, Kevin J. Nowka, Vojin G. Oklobdzija. 56-59 [doi]
• Power-aware partitioned cache architecturesSoontae Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin, E. Geethanjali. 64-67 [doi]
• A low-leakage dynamic multi-ported register file in 0.13mm CMOSAtila Alvandpour, Ram Krishnamurthy, K. Soumyanath, Shekhar Borkar. 68-71 [doi]
• Energy-efficient load and store reuseJun Yang, Rajiv Gupta. 72-75 [doi]
• Compiler support for block bufferingMahmut T. Kandemir, J. Ramanujam, Ugur Sezer. 76-79 [doi]
• Automatic source code specialization for energy reductionEui-Young Chung, Luca Benini, Giovanni De Micheli. 80-83 [doi]
• FV encoding for low-power data I/OJun Yang, Rajiv Gupta. 84-87 [doi]
• Time-to-failure estimation for batteries in portable electronic systemsDaler N. Rakhmatov, Sarma B. K. Vrudhula. 88-91 [doi]
• Architecture strategies for energy-efficient packet forwarding in wireless sensor networksVlasios Tsiatsis, Scott Zimbeck, Mani B. Srivastava. 92-95 [doi]
• Modulation scaling for Energy Aware Communication SystemsCurt Schurgers, Olivier Aberthorne, Mani B. Srivastava. 96-99 [doi]
• Cooling and power consideration for semiconductors into the next centuryChristian Belady. 100-105 [doi]
• Energy efficient Modulation and MAC for Asymmetric RF Microsensor SystemsAndrew Wang, Seong-Hwan Cho, Charles Sodini, Anantha Chandrakasan. 106-111 [doi]
• 1 V, 1.9 GHz mixer using a lateral bipolar transistor in CMOSSong Ye, Koji Yano, C. Andre T. Salama. 112-116 [doi]
• A 60dB, 246MHz CMOS variable gain amplifier for subsampling GSM receiversMohamed Mostafa, Sherif H. K. Embabi, Mostafa Elmala. 117-122 [doi]
• VTCMOS characteristics and its optimum conditions predicted by a compact analytical modelHyunsik Im, T. Inukai, H. Gomyo, T. Hiramoto, T. Sakurai. 123-128 [doi]
• Memory controller policies for DRAM power managementXiaobo Fan, Carla Schlatter Ellis, Alvin R. Lebeck. 129-134 [doi]
• Run-time power estimation in high performance microprocessorsRuss Joseph, Margaret Martonosi. 135-140 [doi]
• Fast, flexible, cycle-accurate energy estimationPhillip Stanley-Marbell, Michael S. Hsiao. 141-146 [doi]
• Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessorsJames Tschanz, Siva Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De. 147-152 [doi]
• Theory and practical implementation of harmonic resonant rail driverJoong-Seok Moon, William C. Athas, Peter A. Beerel. 153-158 [doi]
• A resonant clock generator for single-phase adiabatic systemsConrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou. 159-164 [doi]
• Enchanced multi-threshold (MTCMOS) circuits using variable well biasStephen V. Kosonocky, Michael Immediato, Peter E. Cottrell, Terence B. Hook, Randy W. Mann, Jeff Brown. 165-169 [doi]
• Encodings for high-performance for energy-efficient signalingAlessandro Bogliolo. 170-175 [doi]
• Low-energy for deep-submicron address busesLuca Macchiarulo, Enrico Macii, Massimo Poncino. 176-181 [doi]
• Irredundant address bus encoding for low powerYazdan Aghaghiri, Farzan Fallah, Massoud Pedram. 182-187 [doi]
• Low power address encoding using self-organizing listsMahesh Mamidipaka, Daniel S. Hirschberg, Nikil Dutt. 188-193 [doi]
• Wireless sensor networks: application driver for low power distributed systemsDeborah Estrin. 194 [doi]
• Scaling of stack effect and its application for leakage reductionSiva Narendra, Vivek De, Dimitri Antoniadis, Anantha Chandrakasan, Shekhar Borkar. 195-200 [doi]
• Variable threshold CMOS (VTCMOS) in series connected circuitsTakashi Inukai, Toshiro Hiramoto, Takayasu Sakurai. 201-206 [doi]
• Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICsAli Keshavarzi, Sean Ma, Siva Narendra, B. Bloechel, K. Mistry, T. Ghani, Shekhar Borkar, Vivek De. 207-212 [doi]
• Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit designRongtian Zhang, Kaushik Roy, David B. Janes. 213-218 [doi]
• A self-optimizing embedded microprocessor using a loop table for low powerFrank Vahid, Ann Gordon-Ross. 219-224 [doi]
• Low power pipelining of linear systems: a common operand centric approachDaehong Kim, Dongwan Shin, Kiyoung Choi. 225-230 [doi]
• A system-level energy minimization approach using datapath width optimizationYun Cao, Hiroto Yasuura. 231-236 [doi]
• Energy: efficient instruction dispatch buffer design for superscalar processorsGurhan Kucuk, Kanad Ghose, Dmitry Ponomarev, Peter M. Kogge. 237-242 [doi]
• High density capacitance structures in submicron CMOS for low power RF applicationTirdad Sowlati, Vickram Vathulya, Domine Leenaerts. 243-246 [doi]
• A CMOS VCO architecture suitable for sub-1 volt high-frequency (8.7-10 GHz) RF applicationsAhmed Mostafa, Mourad N. El-Gamal. 247-250 [doi]
• Low-power direct-sequence spread-spectrum modem architecture for distributed wireless sensor networksCharles Chien, Igor Elgorriaga, Charles McConaghy. 251-254 [doi]
• Effects of elevated temperature on tunable near-zero threshold CMOSVjekoslav Svilan, James B. Burr, G. Tyler. 255-258 [doi]
• A sub-1V dual-threshold domino circuit using product-of-sum logicKoji Fujii, Takakuni Douseki, Yuichi Kado. 259-262 [doi]
• Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI designW. Chen, Wei Hwang, Prabhakar Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi. 263-266 [doi]
• Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applicationsNaran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy. 267-270 [doi]
• A profile-based energy-efficient intra-task voltage scheduling algorithm for real-time applicationsDongkun Shin, Jihong Kim. 271-274 [doi]
• Compiler-directed dynamic voltage/frequency scheduling for energy reduction in mircoprocessorsChung-Hsing Hsu, Ulrich Kremer, Michael S. Hsiao. 275-278 [doi]
• Variable voltage task scheduling algorithms for minimizing energyAli Manzak, Chaitali Chakrabarti. 279-282 [doi]
• Design methodology and optimization strategy for dual-VTH scheme using commercially available toolsMasayuki Hirabayashi, Koichi Nose, Takayasu Sakurai. 283-286 [doi]
• Synthesis of low-leakage PD-SOI circuits with body-biasingMario R. Casu, Gianluca Piccinini, Guido Masera, Maurizio Zamboni. 287-290 [doi]
• Low-power technology mapping for mixed-swing logicRob A. Rutenbar, L. Richard Carley, Roberto Zafalon, Nicola Dragone. 291-294 [doi]
• Frequency-domain supply current macro-modelSrinivas Bodapati, Farid N. Najm. 295-298 [doi]
• A low-power, 5-70MHz, 7th-order filter with programmable boost, group delay, and gain using instantaneous compandingRola A. Baki, Mourad N. El-Gamal. 299-304 [doi]
• Optimizing bias-circuit design of cascode operational amplifier for wide dynamic range operationsTakeshi Fukumoto, Hiroyuki Okada, Kazuyuki Nakamura. 305-309 [doi]
• Leakage current cancellation technique for low power switched-capacitor circuitsLouis S. Y. Wong, Shohan Hossain, Andre Walker. 310-315 [doi]
• A 3-pin 1.5 V 550 mW 176 x 144 self-clocked CMOS active pixel image sensorKwang-Bo Cho, Alexander Krymski, Eric R. Fossum. 316-321 [doi]
• Cached-code compression for energy minimization in embedded processorsLuca Benini, Alberto Macii, Alberto Nannarelli. 322-327 [doi]
• Energy efficient turbo decoding for 3G mobileDavid Garrett, Bing Xu, Chris Nicol. 328-333 [doi]
• Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceiversLei Wang, Naresh R. Shanbhag. 334-339 [doi]
• Power reduction through work reuseEmil Talpes, Diana Marculescu. 340-345 [doi]
• Clocking strategies and scannable latches for low power appliacationsVictor V. Zyuban, D. Meltzer. 346-351 [doi]
• Ultra-low power DLMS adaptive filter for hearing aid applicationsHyung-il Kim, Kaushik Roy. 352-357 [doi]
• A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPUSeiji Miura, Kazushige Ayukawa, Takao Watanabe. 358-363 [doi]
• Analysis and implementation of charge recycling for deep sub-micron busesPaul-Peter Sotiriadis, Theodoros Konstantakopoulos, Anantha Chandrakasan. 364-369 [doi]
• Estimation of power distribution in VLSI interconnectsYoungsoo Shin, Takayasu Sakurai. 370-375 [doi]
• Maximum voltage variation in the power distribution network of VLSI circuits with RLC modelsSudhakar Bobba, Ibrahim N. Hajj. 376-381 [doi]
• Battery capacity measurement and analysis using lithium coin cell batterySung Park, Andreas Savvides, Mani B. Srivastava. 382-387 [doi]
• On the interaction of power distribution network with substrateRajendran Panda, Savithri Sundareswaran, David Blaauw. 388-393 [doi]