Abstract is missing.
- Low power requirements for future digital life styleKi Won Lee. 1 [doi]
- Evolution of low power electronics and its future applicationsTsugio Makimoto, Yoshio Sakai. 2-5 [doi]
- A forward body-biased low-leakage SRAM cache: device and architecture considerationsChris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy. 6-9 [doi]
- Reducing translation lookaside buffer active powerLawrence T. Clark, Byungwoo Choi, Michael Wilkerson. 10-13 [doi]
- A power-aware SWDR cell for reducing cache write powerYen-Jen Chang, Chia-Lin Yang, Feipei Lai. 14-17 [doi]
- A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regimeAmit Agarwal, Kaushik Roy. 18-21 [doi]
- Understanding and minimizing ground bounce during mode transition of power gating structuresSuhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel. 22-25 [doi]
- Energy-efficient data scrambling on memory-processor interfacesLuca Benini, Angelo Galati, Alberto Macii, Enrico Macii, Massimo Poncino. 26-29 [doi]
- Analyzing the energy consumption of security protocolsNachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. 30-35 [doi]
- LPBP: low-power basis profile of the Java 2 Micro EditionInseok Choi, Hyung Soo Kim, Heonshik Shin, Naehyuck Chang. 36-39 [doi]
- Estimating influence of data layout optimizations on SDRAM energy consumptionHyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Erik Brockmeyer, Francky Catthoor, Mary Jane Irwin. 40-43 [doi]
- Analysis of discharge techniques for multiple battery systemsRavishankar Rao, Sarma B. K. Vrudhula, Daler N. Rakhmatov. 44-47 [doi]
- A 225 MHz resonant clocked ASIC chipConrad H. Ziesler, Joohee Kim, Visvesh S. Sathe, Marios C. Papaefthymiou. 48-53 [doi]
- Energy recovery clocking scheme and flip-flops for ultra low-energy applicationsMatthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy. 54-59 [doi]
- A semi-custom voltage-island technique and its application to high-speed serial linksJuan Antonio Carballo, Jeffrey L. Burns, Seung-Moon Yoo, Ivan Vo, V. Robert Norman. 60-65 [doi]
- UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSIKyu-won Choi, Abhijit Chatterjee. 72-77 [doi]
- Full chip leakage estimation considering power supply and temperature variationsHaihua Su, Frank Liu, Anirudh Devgan, Emrah Acar, Sani R. Nassif. 78-83 [doi]
- Statistical estimation of leakage current considering inter- and intra-die process variationRajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester. 84-89 [doi]
- Leakage power modeling and optimization in interconnection networksXuning Chen, Li-Shiuan Peh. 90-95 [doi]
- Leakage and leakage sensitivity computation for combinational circuitsEmrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns. 96-99 [doi]
- Efficient techniques for gate leakage estimationRahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown. 100-103 [doi]
- Design methodology for fine-grained leakage control in MTCMOSBenton H. Calhoun, Frank Honoré, Anantha Chandrakasan. 104-109 [doi]
- An MTCMOS design methodology and its application to mobile computingHyo-Sig Won, Kyo-Sun Kim, Kwang-Ok Jeong, Ki Tae Park, Kyu-Myung Choi, Jeong-Taek Kong. 110-115 [doi]
- Optimal body bias selection for leakage improvement and process compensation over different technology generationsCassondra Neau, Kaushik Roy. 116-121 [doi]
- Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologiesBhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar. 122-127 [doi]
- An ASIC design methodology with predictably low leakage, using leakage-immune standard cellsNikhil Jayakumar, Sunil P. Khatri. 128-133 [doi]
- Low-power high-level synthesis for FPGA architecturesDeming Chen, Jason Cong, Yiping Fan. 134-139 [doi]
- ILP-based optimization of sequential circuits for low powerFeng Gao, John P. Hayes. 140-145 [doi]
- Simultaneous Vt selection and assignment for leakage optimizationAnkur Srivastava. 146-151 [doi]
- Effective graph theoretic techniques for the generalized low power binding problemAzadeh Davoodi, Ankur Srivastava. 152-157 [doi]
- Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimizationDavid Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery, Brandon Thompson, Kurt Keutzer. 158-163 [doi]
- Level conversion for dual-supply systemsFujio Ishihara, Farhana Sheikh, Borivoje Nikolic. 164-167 [doi]
- New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technologyKoushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown. 168-171 [doi]
- Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variationSaibal Mukhopadhyay, Kaushik Roy. 172-175 [doi]
- A clock delayed sleep mode domino logic for wide dynamic OR gateKwang-Il Oh, Lee-Sup Kim. 176-179 [doi]
- Strained-si devices and circuits for low-power applicationsKeunwoo Kim, Rajiv V. Joshi, Ching-Te Chuang. 180-183 [doi]
- Low power startup circuits for voltage and current reference with zero steady state currentQadeer Ahmad Khan, Sanjay Kumar Wadhwa, Kulbhushan Misri. 184-188 [doi]
- Reverse-order source/drain formation with double offset spacer (RODOS) for CMOS low-power, high-speed and low-noise amplifiersWoo-Young Choi, Jong Duk Lee, Byung-Gook Park. 189-192 [doi]
- Electric-energy generation using variable-capacitive resonator for power-free LSI: efficiency analysis and fundamental experimentMasayuki Miyazaki, Hidetoshi Tanaka, Goichi Ono, Tomohiro Nagano, Norio Ohkubo, Takayuki Kawahara, Kazuo Yano. 193-198 [doi]
- Temperature and process invariant MOS-based reference current generation circuits for sub-1V operationStephen Tang, Siva Narendra, Vivek De. 199-204 [doi]
- Elements of low power design for integrated systemsSung-Mo Kang. 205-210 [doi]
- Microarchitecture level power and thermal simulation considering temperature dependent leakage modelWeiping Liao, Fei Li, Lei He. 211-216 [doi]
- Reducing power density through activity migrationSeongmoo Heo, Kenneth C. Barr, Krste Asanovic. 217-222 [doi]
- Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noiseMichael D. Powell, T. N. Vijaykumar. 223-228 [doi]
- Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessorsYiran Chen, Kaushik Roy, Cheng-Kok Koh. 229-234 [doi]
- Reducing reorder buffer complexity through selective operand cachingGurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad Ghose. 235-240 [doi]
- Routine based OS-aware microprocessor resource adaptation for run-time operating system power savingTao Li, Lizy Kurian John. 241-246 [doi]
- Ambient intelligence: industrial research on a visionary conceptWerner Weber. 247-251 [doi]
- Reducing data cache energy consumption via cached load/store queueDan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau. 252-257 [doi]
- On load latency in low-power cachesSoontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin, Lizy Kurian John. 258-261 [doi]
- Reducing energy and delay using efficient victim cachesGokhan Memik, Glenn Reinman, William H. Mangione-Smith. 262-265 [doi]
- Low cost instruction cache designs for tag comparison eliminationYoutao Zhang, Jun Yang. 266-269 [doi]
- Lightweight set buffer: low power data cache for multimedia applicationJun Yang, Youtao Zhang. 270-273 [doi]
- Non redundant data cacheCarlos Molina, Carles Aliagas, Montse Garcia, Antonio González, Jordi Tubella. 274-277 [doi]
- A critical analysis of application-adaptive multiple clock processorsEmil Talpes, Diana Marculescu. 278-281 [doi]
- Microprocessor pipeline energy analysisKarthik Natarajan, Heather Hanson, Stephen W. Keckler, Charles R. Moore, Doug Burger. 282-287 [doi]
- B#: a battery emulator and power profiling instrumentPai H. Chou, Chulsung Park, Jae Park, Kien Pham, Jinfeng Liu. 288-293 [doi]
- ESTIMA: an architectural-level power estimator for multi-ported pipelined register filesKavel M. Büyüksahin, Priyadarsan Patra, Farid N. Najm. 294-297 [doi]
- Multivoltage scheduling with voltage-partitioned variable storageAmitabh Menon, S. K. Nandy, Mahesh Mehendale. 298-301 [doi]
- Voltage scheduling under unpredictabilities: a risk management paradigmAzadeh Davoodi, Ankur Srivastava. 302-305 [doi]
- Energy efficient D-TLB and data cache using semantic-aware multilateral partitioningHsien-Hsin S. Lee, Chinnakrishnan S. Ballapuram. 306-311 [doi]
- A selective filter-bank TLB systemJung Hoon Lee, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim. 312-317 [doi]
- Checkpointing alternatives for high performance, power-aware processorsAndreas Moshovos. 318-321 [doi]
- Reducing instruction fetch energy with backwards branch control information and bufferingJude A. Rivers, Sameh W. Asaad, John-David Wellman, Jaime H. Moreno. 322-325 [doi]
- Pipeline stage unification: a low-energy consumption technique for future mobile processorsHajime Shimada, Hideki Ando, Toshio Shimada. 326-329 [doi]
- Energy-efficient instruction set synthesis for application-specific processorsJong-eun Lee, Kiyoung Choi, Nikil D. Dutt. 330-333 [doi]
- A low-power design methodology for high-resolution pipelined analog-to-digital convertersReza Lotfi, Mohammad Taherzadeh-Sani, M. Yaser Azizi, Omid Shoaei. 334-339 [doi]
- A 1-V 1-mW high-speed class AB operational amplifier for high-speed low power pipelined A/D converters using Slew Boost techniqueHesam Amir Aslanzadeh, Saeid Mehrmanesh, Mohammad B. Vahidfar, Amin Quasem Safarian, Reza Lotfi. 340-344 [doi]
- Low-voltage low-power fast-settling CMOS operational transconductance amplifiers for switched-capacitor applicationsMohammad Yavari, Omid Shoaei. 345-348 [doi]
- Low-voltage low-power high dB-linear CMOS exponential function generator using highly-linear V-I converterQuoc-Hoang Duong, Trung-Kien Nguyen, Sang-Gug Lee. 349-352 [doi]
- A new architecture for rail-to-rail input constant-gm CMOS operational transconductance amplifiersMohammad M. Ahmadi, Reza Lotfi. 353-358 [doi]
- A systems approach to molecular electronicsJames R. Heath. 359 [doi]
- Energy-aware architectures for a real-valued FFT implementationAlice Wang, Anantha Chandrakasan. 360-365 [doi]
- A low-power VLSI architecture for turbo decodingSeok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer. 366-371 [doi]
- A mixed-clock issue queue design for globally asynchronous, locally synchronous processor coresVenkata Syam P. Rapaka, Diana Marculescu. 372-377 [doi]
- Power efficient comparators for long arguments in superscalar processorsDmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose. 378-383 [doi]
- The microarchitecture of a low power register fileNam Sung Kim, Trevor N. Mudge. 384-389 [doi]
- Branch prediction on demand: an energy-efficient solutionDaniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado, Michael C. Huang. 390-395 [doi]
- Dynamic voltage scaling algorithm for fixed-priority real-time systems using work-demand analysisWoonseok Kim, Jihong Kim, Sang Lyul Min. 396-401 [doi]
- Exploiting program hotspots and code sequentiality for instruction cache leakage managementJie S. Hu, A. Nadgir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir. 402-407 [doi]
- Power-aware scheduling of conditional task graphs in real-time multiprocessor systemsDongkun Shin, Jihong Kim. 408-413 [doi]
- Exploiting compiler-generated schedules for energy savings in high-performance processorsMadhavi Gopal Valluri, Lizy Kurian John, Heather Hanson. 414-419 [doi]
- Energy-aware memory allocation in heterogeneous non-volatile memory systemsHyung Gyu Lee, Naehyuck Chang. 420-423 [doi]
- Energy characterization of a tiled architecture processor with on-chip networksJason Sungtae Kim, Michael Bedford Taylor, Jason E. Miller, David Wentzlaff. 424-427 [doi]
- Low power RF IC design for wireless communicationDomine Leenaerts. 428-433 [doi]
- A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology on high resistivity substrateJonghae Kim, Jean-Olivier Plouchart, Noah Zamdmer, Melanie Sherony, Yue Tan, Meeyoung Yoon, Robert Trzcinski, Mohamed Talbi, John Safran, Asit Ray, Lawrence F. Wagner. 434-439 [doi]
- A 0.123 mW 7.25 GHz static frequency divider by 8 in a 120-nm SOI technologyJean-Olivier Plouchart, Jonghae Kim, Hector Recoules, Noah Zamdmer, Yue Tan, Melanie Sherony, Asit Ray, Lawrence F. Wagner. 440-442 [doi]
- A 0.75-mW analog processor IC for wireless biosignal monitorChih-Jen Yen, Mely Chen Chi, Wen-Yaw Chung, Shing-Hao Lee. 443-448 [doi]
- Integrated DC-DC converter design for improved WCDMA power amplifier efficiency in SiGe BiCMOS technologyDrew Guckenberger, Kevin T. Kornegay. 449-454 [doi]
- A novel high frequency, high-efficiency, differential class-E power amplifier in 0.18mum CMOSPayam Heydari, Ying Zhang. 455-458 [doi]
- Energy optimization techniques in cluster interconnectsEun Jung Kim, Ki Hwan Yum, Greg M. Link, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Mazin S. Yousif, Chita R. Das. 459-464 [doi]
- Uncertainty-based scheduling: energy-efficient ordering for tasks with variable execution timeFlavius Gruian, Krzysztof Kuchcinski. 465-468 [doi]
- Energy efficiency and fairness tradeoffs in multi-resource, multi-tasking embedded systemsSung I. Park, Vijay Raghunathan, Mani B. Srivastava. 469-474 [doi]
- Low power coordination in wireless ad-hoc networksFarinaz Koushanfar, Abhijit Davare, Dai Tho Nguyen, Miodrag Potkonjak, Alberto L. Sangiovanni-Vincentelli. 475-480 [doi]
- An environmental energy harvesting framework for sensor networksAman Kansal, Mani B. Srivastava. 481-486 [doi]