Abhitosh Vais - researchr alias

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Viewing Publication 1 - 6 from 6

2022

III-V HBTs on 300 mm Si substrates using merged nano-ridges and its application in the study of impact of defects on DC and RF performanceAbhitosh Vais, Sachin Yadav, Yves Mols, Bjorn Vermeersch, Komal Vondkar Kodandarama, Marina Baryshnikova, G. Mannaert, R. Alcotte, Geert Boccardi, Piet Wambacq, Bertrand Parvais, R. Langer, Bernardette Kunert, Nadine Collaert. essderc 2022: 261-264 [doi]

2021

A defect characterization technique for the sidewall surface of Nano-ridge and Nanowire based Logic and RF technologiesAbhitosh Vais, B. Hsu, O. Syshchyk, H. Yu, AliReza Alian, Y. Mols, K. V. Kodandarama, B. Kunert, Niamh Waldron, Eddy Simoen, Nadine Collaert. irps 2021: 1-5 [doi]

2018

Impact of slow and fast oxide traps on In0.53Ga0.47As device operation studied using CET mapsV. Putcha, Jacopo Franco, Abhitosh Vais, Ben Kaczer, S. Sioncke, Dimitri Linten, Guido Groeseneken. irps 2018: 5 [doi]

2016

2015

The relationship between border traps characterized by AC admittance and BTI in III-V MOS devicesAbhitosh Vais, Koen Martens, J. Franco, D. Lin, A. Alian, Philippe Roussel, S. Sioncke, Nadine Collaert, Aaron Thean, Marc M. Heyns, Guido Groeseneken, Kristin De Meyer. irps 2015: 5 [doi]

2014

0.47As MOS capacitors from capacitance-voltage characteristics measured at various temperaturesChunmeng Dou, Dennis Lin, Abhitosh Vais, Tsvetan Ivanov, Han-Ping Chen, Koen Martens, Kuniyuki Kakushima, Hiroshi Iwai, Yuan Taur, Aaron Thean, Guido Groeseneken. mr, 54(4):746-754, 2014. [doi]

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