Journal: IEEE Design & Test of Computers

Volume 20, Issue 5

1 -- 0Rajesh Gupta. At-Speed Testing: A Shared Red Brick between Design and Test
6 -- 7Kenneth M. Butler, Kwang-Ting (Tim) Cheng, Li-C. Wang. Guest Editors Introduction: Speed Test and Speed Binning for Complex ICs
8 -- 16Kee Sup Kim, Subhasish Mitra, Paul G. Ryan. Delay Defect Characteristics and Testing Strategies
17 -- 25Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli. High-Frequency, At-Speed Scan Testing
26 -- 33Stephen Pateras. Achieving At-Speed Structural Test
34 -- 40Alfred L. Crouch, John C. Potter, Jason Doege. AC Scan Path Selection for Physical Debugging
41 -- 45Bruce D. Cory, Rohit Kapur, Bill Underwood. Speed Binning with Path Delay Test in 150-nm Technology
46 -- 53Robert Madge, Brady Benware, W. Robert Daasch. Obtaining High Defect Coverage for Frequency-Dependent Defects in Complex ASICs
54 -- 0Robert C. Aitken, Gordon W. Roberts. ITC 2003: Breaking Test Interface Bottlenecks
55 -- 57Gordon W. Roberts, Robert C. Aitken. ITC Highlights
58 -- 66Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian. Embedded Deterministic Test for Low-Cost Manufacturing
67 -- 75Darren Anand, Bruce Cowan, Owen Farnsworth, Peter Jakobsen, Steven F. Oakland, Michael Ouellette, Donald L. Wheater. An On-Chip Self-Repair Calculation and Fusing Methodology
76 -- 83Bill Eklow, Carl Barnhart, Kenneth P. Parker. IEEE 1149.6: A Boundary-Scan Standard for Advanced Digital Networks
84 -- 89Peter C. Maxwell. Wafer-Package Test Mix for Optimal Defect Detection and Test Time Savings
90 -- 93. ARM Twisting with Sir Robin: An Interview with ARM Chairman Sir Robin Saxby
94 -- 96Jay Lawrence. Orthogonality of Verilog Data Types and Object Kinds
97 -- 99. Conference Reports
100 -- 0. DATC Newsletter
102 -- 103. TTTC Newsletter
104 -- 0Scott Davidson. All I Know I Learned at ITC