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    Journal: IEEE Design & Test of Computers

    Volume 20, Issue 6

    1 -- 0Rajesh Gupta. From the EIC: The changing face of IC design and its industry
    5 -- 8Soha Hassoun, Yong-Bin Kim, Fabrizio Lombardi. Guest Editors Introduction: Clockless VLSI Systems
    9 -- 17Alain J. Martin, Mika Nyström, Catherine G. Wong. Three Generations of Asynchronous Microprocessors
    18 -- 24Stephen H. Unger. Reducing Power Dissipation, Delay, and Area in Logic Circuits by Narrowing Transistors
    26 -- 36Satish K. Bandapati, Scott C. Smith, Minsu Choi. Design and Characterization of Null Convention Self-Timed Multipliers
    38 -- 43Steve Masteller, Lief Sorenson. Cycle Decomposition in NCL
    44 -- 50Juha Plosila, Tiberiu Seceleanu, Pasi Liljeberg. Implementation of a Self-Timed Segmented Bus
    51 -- 58Woo Jin Kim, Yong-Bin Kim. Automating Wave-Pipelined Circuit Design
    59 -- 75Alberto L. Sangiovanni-Vincentelli. The Tides of EDA
    76 -- 85. Fabless or IDM? What the Future Holds for Both: An Interview with Cirrus Logic Chairman, Michael L. Hackworth
    86 -- 95. What Is the Next Implementation Fabric?
    96 -- 97Andrew B. Kahng. How much variability can designers tolerate?
    98 -- 99Wolfgang Roethig. New advanced library format standard approved
    100 -- 102Eric Dupont, Grant Martin. Panel Summaries
    103 -- 0Vladimir Hahanov, Raimund Ubar. Conference Reports
    104 -- 105. Test Technology TC Newsletter
    106 -- 0. Design Automation Technical Committee Newsletter
    108 -- 119. 2003 Annual Index IEEE Design & Test of Computers Volume 20
    120 -- 0Suhwan Kim, Conrad H. Ziesler. A clockless future for systems on chip

    Volume 20, Issue 5

    1 -- 0Rajesh Gupta. At-Speed Testing: A Shared Red Brick between Design and Test
    6 -- 7Kenneth M. Butler, Kwang-Ting (Tim) Cheng, Li-C. Wang. Guest Editors Introduction: Speed Test and Speed Binning for Complex ICs
    8 -- 16Kee Sup Kim, Subhasish Mitra, Paul G. Ryan. Delay Defect Characteristics and Testing Strategies
    17 -- 25Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli. High-Frequency, At-Speed Scan Testing
    26 -- 33Stephen Pateras. Achieving At-Speed Structural Test
    34 -- 40Alfred L. Crouch, John C. Potter, Jason Doege. AC Scan Path Selection for Physical Debugging
    41 -- 45Bruce D. Cory, Rohit Kapur, Bill Underwood. Speed Binning with Path Delay Test in 150-nm Technology
    46 -- 53Robert Madge, Brady Benware, W. Robert Daasch. Obtaining High Defect Coverage for Frequency-Dependent Defects in Complex ASICs
    54 -- 0Robert C. Aitken, Gordon W. Roberts. ITC 2003: Breaking Test Interface Bottlenecks
    55 -- 57Gordon W. Roberts, Robert C. Aitken. ITC Highlights
    58 -- 66Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian. Embedded Deterministic Test for Low-Cost Manufacturing
    67 -- 75Darren Anand, Bruce Cowan, Owen Farnsworth, Peter Jakobsen, Steven F. Oakland, Michael Ouellette, Donald L. Wheater. An On-Chip Self-Repair Calculation and Fusing Methodology
    76 -- 83Bill Eklow, Carl Barnhart, Kenneth P. Parker. IEEE 1149.6: A Boundary-Scan Standard for Advanced Digital Networks
    84 -- 89Peter C. Maxwell. Wafer-Package Test Mix for Optimal Defect Detection and Test Time Savings
    90 -- 93. ARM Twisting with Sir Robin: An Interview with ARM Chairman Sir Robin Saxby
    94 -- 96Jay Lawrence. Orthogonality of Verilog Data Types and Object Kinds
    97 -- 99. Conference Reports
    100 -- 0. DATC Newsletter
    102 -- 103. TTTC Newsletter
    104 -- 0Scott Davidson. All I Know I Learned at ITC

    Volume 20, Issue 4

    3 -- 0Rajesh Gupta. From the Editor in Chief: Addressing Problems of the Large
    4 -- 14Ravi Hosabettu, Ganesh Gopalakrishnan, Mandayam K. Srivas. A Practical Methodology for Verifying Pipelined Microarchitectures
    16 -- 21João P. Marques Silva, Luís Guerra e Silva. Solving Satisfiability in Combinational Circuits
    22 -- 30Ozgur Sinanoglu, Alex Orailoglu. Compacting Test Responses for Deeply Embedded SoC Cores
    32 -- 39Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Yervant Zorian. A Hierarchical Infrastructure for SoC Test Management
    40 -- 47Ian G. Harris. Fault Models and Test Generation for Hardware-Software Covalidation
    48 -- 55Nicola Nicolici, Bashir M. Al-Hashimi. Power-Conscious Test Synthesis and Scheduling
    56 -- 64Dionisios N. Pnevmatikatos, Ioannis Sourdis, Kyriakos Vlachos. An Efficient, Low-Cost I/O Subsystem for Network Processors
    66 -- 81. Embedded Memories for the Future
    82 -- 84David I. Rich. The Evolution of SystemVerilog
    86 -- 88Carl Pixley, Juan Antonio Carballo. Panel Summaries
    89 -- 0. McCluskey Awarded TTTC Lifetime Contribution Medal
    90 -- 91. TTTC Newsletter
    93 -- 0. DATC Newsletter
    95 -- 96Bill Mann. Test s Evolving Mission

    Volume 20, Issue 3

    1 -- 0Rajesh Gupta. From the Editor in Chief: A Powerful Issue!
    5 -- 6Sani R. Nassif, Soha Hassoun. Guest Editors Introduction: On-Chip Power Distribution Networks
    7 -- 15Sachin S. Sapatnekar, Haihua Su. Analysis and Optimization of Power Grids
    16 -- 22Rajendran Panda, Savithri Sundareswaran, David Blaauw. Impact of Low-Impedance Substrate on Power Supply Integrity
    24 -- 31Hui Zheng, Byron Krauter, Lawrence T. Pileggi. Electrical Modeling of Integrated-Package Power and Ground Distributions
    32 -- 39Arindam Mukherjee, Malgorzata Marek-Sadowska. Clock and Power Gating with Timing Closure
    40 -- 47Ed Grochowski, David Ayers, Vivek Tiwari. Microarchitectural dI/dt Control
    49 -- 0Yervant Zorian. Guest Editor s Introduction: Advances in Infrastructure IP
    50 -- 57Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto. Online Self-Repair of FIR Filters
    58 -- 66Yervant Zorian, Samvel K. Shoukourian. Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield
    68 -- 77Md. Saffat Quasem, Zhigang Jiang, Sandeep K. Gupta. Benefits of a SoC-Specific Test Methodology
    78 -- 87C. J. Clark, Mike Ricchetti. Infrastructure IP for Configuration and Test of Boards and Systems
    88 -- 89Luciano Lavagno, Limor Fix. DAC Highlights
    90 -- 96Alberto L. Sangiovanni-Vincentelli. DAC Turns 40!
    97 -- 98Pat O. Pistilli. DAC: Serving the EDA Community for 40 Years
    99 -- 100Ronald A. Rohrer. DAC, Moore s Law Still Drive EDA
    101 -- 102Giovanni De Micheli. CASS Brings Publishing to Its DAC Partnership
    104 -- 107Soha Hassoun, Geert Janssen. First CADathlon Programming Contest held at 2002 ICCAD
    108 -- 0Yervant Zorian. IEEE CASS becomes D&T Copublisher
    110 -- 111Andrew B. Kahng. Bringing down NRE
    112 -- 113Peter J. Ashenden. VHDL-200X: The Next Revision
    114 -- 0Tom Anderson. Who Cares about System Verification?
    115 -- 0. Conference Reports
    116 -- 117. TTTC Newsletter
    118 -- 0. DATC Newsletter
    120 -- 0Mary Jane Irwin. Power-Aware Designers at Odds with Power Grid Designers?

    Volume 20, Issue 2

    1 -- 0Rajesh Gupta. From the Editor in Chief: Full Circle?
    5 -- 7Monica Lobetti Bodoni, Ben Bennetts. Guest Editors Introduction: Board Test
    8 -- 18Erik Jan Marinissen, Bart Vermeulen, Henk D. L. Hollmann, Ben Bennetts. Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint
    20 -- 25Bradford G. Van Treuren, José M. Miranda. Embedded Boundary Scan
    26 -- 30Mahnaz Salamati, Dag Stranneby. Electromagnetic Signatures as a Tool for Connectionless Test
    32 -- 39Uros Kac, Franc Novak, Florence Azaïs, Pascal Nouet, Michel Renovell. Extending IEEE Std. 1149.4 Analog Boundary Modules to Enhance Mixed-Signal Test
    40 -- 47Nur Engin, Hans G. Kerkhoff. Fast Fault Simulation for Nonlinear Analog Circuits
    48 -- 55Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou. A Design-for-Verification Technique for Functional Pattern Reduction
    56 -- 64Miroslav Cupák, Francky Catthoor, Hugo De Man. Efficient System-Level Functional Verification Methodology for Multimedia Applications
    65 -- 75João M. P. Cardoso, Horácio C. Neto. Compilation for FPGA-Based Reconfigurable Hardware
    76 -- 87. Test Data Compression
    90 -- 91Carol Stolicny. ITC 2002 Panels: Part 2
    93 -- 0. DATC Newsletter
    94 -- 95. TTTC Newsletter
    96 -- 0Kenneth P. Parker. Testing for what?

    Volume 20, Issue 1

    1 -- 0Rajesh Gupta. From the Editor in Chief: Twenty years!
    6 -- 7Alex Orailoglu, Alexander V. Veidenbaum. Guest Editors Introduction: Application-Specific Microprocessors
    8 -- 16Wolfgang Raab, Nico Brüls, J. A. Ulrich Hachmann, Jens Harnisch, Ulrich Ramacher, Christian Sauer, Axel Techmer. A 100-GOPS Programmable Processor for Vehicle Vision Systems
    18 -- 25Peter Petrov, Alex Orailoglu. Application-Specific Instruction Memory Customizations for Power-Efficient Embedded Processors
    26 -- 33Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt. Compilation Approach for Coarse-Grained Reconfigurable Architectures
    34 -- 41Oliver Wahlen, Manuel Hohenauer, Rainer Leupers, Heinrich Meyr. Instruction Scheduler Generation for Retargetable Compilation
    42 -- 50Jörg E. Vollrath. Testing and Characterization of SDRAMs
    51 -- 59Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski. 2D Test Sequence Generators
    60 -- 67Florence Azaïs, Yves Bertrand, Michel Renovell, André Ivanov, Sassan Tabatabaei. An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs
    68 -- 75Jean Michel Daga, Caroline Papaix, Marc Merandat, Stephane Ricard, Giuseppe Medulla, Jeanine Guichaoua, Daniel Auvergne. Design Techniques for EEPROMs Embedded in Portable Systems on Chips
    76 -- 84Luigi Carro, Marcelo Negreiros, Gabriel Parmegiani Jahn, Adão Antônio de Souza Jr., Denis Teixeira Franco. Circuit-Level Considerations for Mixed-Signal Programmable Components
    86 -- 87Andrew B. Kahng. Error Tolerance
    88 -- 90Carol Stolicny. ITC 2002 Panels
    91 -- 92Peter J. Ashenden. Boundary Scan Test Standards
    92 -- 0Ahmed Amine Jerraya. Hot Topics at HLDVT 02
    93 -- 0. DATC Newsletter
    94 -- 95. TTTC Newsletter
    96 -- 0Frank Vahid. Making the Best of Those Extra Transistors
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