| 121 | -- | 132 | . SOI technology for the GHz era |
| 133 | -- | 168 | H.-S. Philip Wong. Beyond the conventional transistor |
| 169 | -- | 186 | Edward J. Nowak. Maintaining the benefits of CMOS scaling when scaling bogs down |
| 187 | -- | 222 | Jack A. Mandelman, Robert H. Dennard, Gary B. Bronner, John K. DeBrosse, Rama Divakaruni, Yujun Li, Carl J. Raden. Challenges and future directions for the scaling of dynamic random-access memory (DRAM) |
| 223 | -- | 234 | Ravi Nair. Effect of increasing chip density on the evolution of computer architectures |
| 235 | -- | 344 | David J. Frank. Power-constrained CMOS scaling limits |
| 245 | -- | 264 | James D. Meindl, Jeffrey A. Davis, Payman Zarkesh-Ha, Chirag S. Patel, Kevin P. Martin, Paul A. Kohl. Interconnect opportunities for gigascale integration |
| 265 | -- | 286 | James H. Stathis. Reliability limits for the gate insulator in CMOS technology |
| 287 | -- | 298 | Ernest Y. Wu, Edward J. Nowak, Alex Vayshenker, Wing L. Lai, David L. Harmon. CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics |
| 299 | -- | 316 | Carlton M. Osburn, Indong Kim, Sungkee Han, Indranil De, Kam F. Yee, Shyam Gannavaram, Sungjoo Lee, Chung-Ho Lee, Zhijiong J. Luo, Wenjuan Zhu, John R. Hauser, Dim-Lee Kwong, Gerald Lucovsky, T. P. Ma, Mehmet C. Öztürk. Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go? |
| 317 | -- | 338 | Paul D. Agnello. Process requirements for continued scaling of CMOS-the need and prospects for atomic-level manipulation |
| 339 | -- | 346 | Mark E. Law. Process modeling for future technologies |
| 347 | -- | 358 | Anthony Lochtefeld, Ihsan J. Djomehri, Ganesh Samudra, Dimitri A. Antoniadis. New insights into carrier transport in n-MOSFETs |