| 399 | -- | 0 | Masao Nakaya. Special Section on Advanced Technologies in Digital LSIs and Memories |
| 399 | -- | 0 | Masao Nakaya. Special Section on Advanced Technologies in Digital LSIs and Memories |
| 400 | -- | 409 | Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato. A Low-Power Instruction Issue Queue for Microprocessors |
| 410 | -- | 417 | Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami. Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems |
| 418 | -- | 431 | Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami. Temperature-Aware Configurable Cache to Reduce Energy in Embedded Systems |
| 432 | -- | 439 | Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara. Power-Aware Compiler Controllable Chip Multiprocessor |
| 440 | -- | 448 | Yibo Fan, Takeshi Ikenaga, Satoshi Goto. Reconfigurable Variable Block Size Motion Estimation Architecture for Search Range Reduction Algorithm |
| 449 | -- | 456 | Qin Liu, Seiichiro Hiratsuka, Kazunori Shimizu, Shinsuke Ushiki, Satoshi Goto, Takeshi Ikenaga. A 41 mW VGA@30 fps Quadtree Video Encoder for Video Surveillance Systems |
| 457 | -- | 464 | Yuichiro Murachi, Yuki Fukuyama, Ryo Yamamoto, Junichi Miyakoshi, Hiroshi Kawaguchi, Hajime Ishihara, Masayuki Miyama, Yoshio Matsuda, Masahiko Yoshimoto. A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition |
| 465 | -- | 478 | Yuichiro Murachi, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto. A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer |
| 479 | -- | 486 | Masanori Hariyama, Naoto Yokoyama, Michitaka Kameyama. Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling |
| 487 | -- | 496 | Nicola E. L Insalata, Sergio Saponara, Luca Fanucci, Pierangelo Terreni. Automatic Synthesis of Cost Effective FFT/IFFT Cores for VLSI OFDM Systems |
| 497 | -- | 508 | Hamid Noori, Farhad Mehdipour, Koji Inoue, Kazuaki Murakami. A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom Instructions |
| 509 | -- | 516 | Akihiro Nakamura, Masahide Kawarasaki, Kouta Ishibashi, Masaya Yoshikawa, Takeshi Fujino. Regular Fabric of Via Programmable Logic Device Using EXclusive-or Array (VPEX) for EB Direct Writing |
| 517 | -- | 525 | Hasitha Muthumala Waidyasooriya, Weisheng Chong, Masanori Hariyama, Michitaka Kameyama. Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment |
| 526 | -- | 533 | Shinya Kajiyama, Ken ichiro Sonoda, Kazuo Otsuga, Hideaki Kurata, Kiyoshi Ishikawa. A Design of Constant-Charge-Injection Programming Scheme for AG-AND Flash Memories Using Array-Level Analytical Model |
| 534 | -- | 542 | Shin-ichi O uchi, Meishoku Masahara, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Kunihiro Sakamoto, Toshihiro Sekigawa, Hanpei Koike, Eiichi Suzuki. FinFET-Based Flex-Vth SRAM Design for Drastic Standby-Leakage-Current Reduction |
| 543 | -- | 552 | Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto. A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing |
| 553 | -- | 561 | Tadayoshi Enomoto, Suguru Nagayama, Hiroaki Shikano, Yousuke Hagiwara. Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array |
| 562 | -- | 570 | Kenta Yamada, Noriaki Oda. Statistical Corner Conditions of Interconnect Delay (Corner LPE Specifications) |
| 571 | -- | 580 | Xu Zhang, Xiaohong Jiang, Susumu Horiguchi. Redundant Vias Insertion for Performance Enhancement in 3D ICs |
| 581 | -- | 588 | Kazuyasu Mizusawa, Naoya Onizawa, Takahiro Hanyu. Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling |
| 589 | -- | 594 | Masatomo Miura, Takahiro Hanyu. Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation |
| 595 | -- | 606 | Hyunjeong Park, Hyungsoo Kim, Jun So Pak, Changwook Yoon, Kyoungchoul Koo, Joungho Kim. Co-modeling, Experimental Verification, and Analysis of Chip-Package Hierarchical Power Distribution Network |
| 607 | -- | 614 | Yasuhiko Tamura. TM Plane Wave Reflection and Transmission from a One-Dimensional Random Slab |
| 615 | -- | 624 | Yoshio Inasawa, Shinji Kuroda, Kenji Kusakabe, Izuru Naito, Yoshihiko Konishi, Shigeru Makino, Makio Tsuchiya. Design Method for a Low-Profile Dual-Shaped Reflector Antenna with an Elliptical Aperture by the Suppression of Undesired Scattering |
| 625 | -- | 630 | Jhin-Fang Huang, Shih-Huang Wu. Planar T-Shaped Monopole Antenna for WLAN/WiMAX Applications |
| 631 | -- | 637 | Shun Nakagawa, Koichi Narahara. Characterization of Two-Stage Composite Right- and Left-Handed Transmission Lines |
| 638 | -- | 646 | Shinya Watanabe, Akitoshi Taniguchi, Kota Saito, Osamu Hashimoto, Toshifumi Saito, Hiroshi Kurihara. Computer Simulation about Temperature Distribution of an EM-Wave Absorber Using a Coupled Analysis Method |
| 647 | -- | 654 | Masakazu Aoki, Shin-ichi Ohkawa, Hiroo Masuda. Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis |
| 655 | -- | 661 | Yusuke Ohtomo, Hiroshi Koizumi, Kazuyoshi Nishimura, Masafumi Nogawa. A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI |
| 662 | -- | 665 | Luis H. C. Ferreira, Tales Cleber Pimenta, Robson L. Moreno. An Ultra-Low-Voltage Ultra-Low-Power Weak Inversion Composite MOS Transistor: Concept and Applications |
| 666 | -- | 669 | Hua-Pin Chen, Wan-Shing Yang. High-Input and Low-Output Impedance Voltage-Mode Universal DDCC and FDCCII Filter |
| 670 | -- | 672 | Kicheol Kim, Youbean Kim, Incheol Kim, HyeonUk Son, Sungho Kang. A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters |