| 97 | -- | 99 | Veljko M. Milutinovic, Mateo Valero. Enhancing and Exploiting the Locality |
| 100 | -- | 110 | Jih-Kwon Peir, Windsor W. Hsu, Alan Jay Smith. Functional Implementation Techniques for CPU Cache Memories |
| 111 | -- | 120 | Eric Rotenberg, Steve Bennett, James E. Smith. A Trace Cache Microarchitecture and Evaluation |
| 121 | -- | 133 | Doug Joseph, Dirk Grunwald. Prefetching Using Markov Predictors |
| 134 | -- | 141 | Chi-Keung Luk, Todd C. Mowry. Automatic Compiler-Inserted Prefetching for Pointer-Based Applications |
| 142 | -- | 149 | Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau. Augmenting Loop Tiling with Data Alignment for Improved Cache Performance |
| 150 | -- | 158 | Olivier Temam. An Algorithm for Optimally Exploiting Spatial and Temporal Locality in Upper Memory Levels |
| 159 | -- | 167 | Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhary. Improving Cache Locality by a Combination of Loop and Data Transformation |
| 168 | -- | 175 | John Kalamatianos, Alireza Khalafi, David R. Kaeli, Waleed Meleis. Analysis of Temporal-Based Program Behavior for Improved Instruction Cache Performance |
| 176 | -- | 184 | Hantak Kwak, Ben Lee, Ali R. Hurson, Suk-Han Yoon, Woo-Jong Hahn. Effects of Multithreading on Cache Performance |
| 185 | -- | 192 | Nigel P. Topham, Antonio González. Randomized Cache Placement for Eliminating Conflicts |
| 193 | -- | 204 | Sanjay J. Patel, Daniel H. Friendly, Yale N. Patt. Evaluation of Design Options for the Trace Cache Fetch Mechanism |
| 205 | -- | 217 | Mark Heinrich, Vijayaraghavan Soundararajan, John L. Hennessy, Anoop Gupta. A Quantitative Analysis of the Performance and Scalability of Distributed Shared Memory |
| 218 | -- | 226 | Vijay S. Pai, Parthasarathy Ranganathan, Hazim Abdel-Shafi, Sarita V. Adve. The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors |
| 227 | -- | 235 | Seungjoon Park, David L. Dill. An Executable Specification and Verifier for Relaxed Memory Order |
| 236 | -- | 244 | Donglai Dai, Dhabaleswar K. Panda. Exploiting the Benefits of Multiple-Path Network DSM Systems: Architectural Alternatives and Performance Evaluation |
| 245 | -- | 255 | Maged M. Michael, Ashwini K. Nanda, Beng-Hong Lim. Coherence Controller Architectures for Scalable Shared-Memory Multiprocessors |
| 256 | -- | 264 | Zheng Zhang, Marcelo H. Cintra, Josep Torrellas. Excel-NUMA: Toward Programmability, Simplicity, and High Performance |