| 2613 | -- | 2625 | Arthur Nieuwoudt, Yehia Massoud. Variability-Aware Multilevel Integrated Spiral Inductor Synthesis |
| 2626 | -- | 2637 | Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino. Reducing Conflict Misses by Application-Specific Reconfigurable Indexing |
| 2638 | -- | 2649 | Natasa Miskov-Zivanov, Diana Marculescu. Circuit Reliability Analysis Using Symbolic Techniques |
| 2650 | -- | 2662 | Chantana Chantrapornchai, Wanlop Surakampontorn, Edwin Hsing-Mean Sha. Design Exploration With Imprecise Latency and Register Constraints |
| 2663 | -- | 2673 | Milenko Drinic, Darko Kirovski, Seapahn Megerian, Miodrag Potkonjak. Latency-Guided On-Chip Bus-Network Design |
| 2674 | -- | 2686 | Jie-Hong Roland Jiang, Robert K. Brayton. Retiming and Resynthesis: A Complexity Perspective |
| 2687 | -- | 2696 | Darko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak, Jason Cong. Protecting Combinational Logic Synthesis Solutions |
| 2697 | -- | 2711 | Le Cai, Nathaniel Pettis, Yung-Hsiang Lu. Joint Power Management of Memory and Disk Under Performance Constraints |
| 2712 | -- | 2725 | Ali Iranli, Massoud Pedram. Cycle-Based Decomposition of Markov Chains With Applications to Low-Power Synthesis and Sequence Compaction for Finite State Machines |
| 2726 | -- | 2736 | Yuantao Peng, Xun Liu. An Efficient Low-Power Repeater-Insertion Scheme |
| 2737 | -- | 2746 | Ravishankar Rao, Sarma B. K. Vrudhula. Energy-Optimal Speed Control of a Generic Device |
| 2747 | -- | 2756 | Puneet Gupta, Andrew B. Kahng, Chul-Hong Park, Kambiz Samadi, Xu Xu. Wafer Topography-Aware Optical Proximity Correction |
| 2757 | -- | 2764 | Hessa Al-Junaid, Tom J. Kazmierski, Peter R. Wilson, Jerzy Baranowski. Timeless Discretization of Magnetization Slope in the Modeling of Ferromagnetic Hysteresis |
| 2765 | -- | 2774 | Aditya Bansal, Bipul Chandra Paul, Kaushik Roy. An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping |
| 2775 | -- | 2783 | Luis Miguel Silveira, Joel R. Phillips. Resampling Plans for Sample Point Selection in Multipoint Model-Order Reduction |
| 2784 | -- | 2794 | Muhammet Mustafa Ozdal, Martin D. F. Wong. A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards |
| 2795 | -- | 2805 | Lei Cheng, Martin D. F. Wong. Floorplan Design for Multimillion Gate FPGAs |
| 2806 | -- | 2819 | Andrew B. Kahng, Sherief Reda. Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking |
| 2820 | -- | 2832 | Kaviraj Chopra, Sarma B. K. Vrudhula. Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States |
| 2833 | -- | 2842 | Xiaochun Duan, Kartikeya Mayaram. Frequency-Domain Simulation of Ring Oscillators With a Multiple-Probe Method |
| 2843 | -- | 2851 | Xiaochun Duan, Kartikeya Mayaram. Robust Simulation of High-Q Oscillators Using a Homotopy-Based Harmonic Balance Method |
| 2852 | -- | 2867 | Peng Li. Statistical Sampling-Based Parametric Analysis of Power Grids |
| 2868 | -- | 2881 | Zhao Li, C.-J. Richard Shi. A Quasi-Newton Preconditioned Newton-Krylov Method for Robust and Efficient Time-Domain Simulation of Integrated Circuits With Strong Parasitic Couplings |
| 2882 | -- | 2893 | Pu Liu, Hang Li, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang. Fast Thermal Simulation for Runtime Temperature Tracking and Management |
| 2894 | -- | 2903 | Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam. Reducing Structural Bias in Technology Mapping |
| 2904 | -- | 2918 | Mehrdad Reshadi, Bita Gorjiara, Nikil D. Dutt. Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators |
| 2919 | -- | 2933 | Jingcao Hu, Ümit Y. Ogras, Radu Marculescu. System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design |
| 2934 | -- | 2943 | Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy. A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor |
| 2944 | -- | 2953 | Fei Su, Krishnendu Chakrabarty. Defect Tolerance Based on Graceful Degradation and Dynamic Reconfiguration for Digital Microfluidics-Based Biochips |
| 2954 | -- | 2964 | Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi. Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model |
| 2965 | -- | 2975 | Debjit Sinha, Hai Zhou. Statistical Timing Analysis With Coupling |
| 2976 | -- | 2988 | Wei-Shen Wang, Michael Orshansky. Path-Based Statistical Timing Analysis Handling Arbitrary Delay Correlations: Theory and Implementation |
| 2989 | -- | 2996 | Zaid Al-Ars, Said Hamdioui, A. J. van de Goor, Sultan M. Al-Harbi. Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs |
| 2996 | -- | 3004 | Mario R. Casu, Luca Macchiarulo. Floorplanning With Wire Pipelining in Adaptive Communication Channels |
| 3004 | -- | 3009 | Ruiming Chen, Hai Zhou. An Efficient Data Structure for Maxplus Merge in Dynamic Programming |
| 3010 | -- | 3016 | Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava. Probabilistic Evaluation of Solutions in Variability-Driven Optimization |
| 3017 | -- | 3025 | Mongkol Ekpanyapong, Michael B. Healy, Sung Kyu Lim. Profile-Driven Instruction Mapping for Dataflow Architectures |
| 3026 | -- | 3035 | Stelios Neophytou, Maria K. Michael, Spyros Tragoudas. Functions for Quality Transition-Fault Tests and Their Applications in Test-Set Enhancement |
| 3035 | -- | 3042 | Xiren Wang, Wenjian Yu, Zeyi Wang. Efficient Direct Boundary Element Method for Resistance Extraction of Substrate With Arbitrary Doping Profile |
| 3042 | -- | 3044 | Hong Li, Wen-Yan Yin, Junfa Mao. Comments on Modeling of Metallic Carbon-Nanotube Interconnects for Circuit Simulations and a Comparison With Cu Interconnects for Sealed Technologies |