| 0 | -- | 0 | Fadi J. Kurdahi. Linking Behavioral, Structural, and Physical Models of Hardware |
| 111 | -- | 124 | Massoud Pedram, Narasimha B. Bhat, Ernest S. Kuh. Combining Technology Mapping With Layout |
| 125 | -- | 140 | Mandalagiri S. Chandrasekhar, Robert H. McCharles, David E. Wallace. Effective Coupling Between Logic Synthesis and Layout Tools for Synthesis of Area and Speed-Efficient Circuits |
| 141 | -- | 153 | Akhilesh Tyagi. Statistical Module Level Area and Delay Estimation |
| 155 | -- | 165 | Nikil D. Dutt, Pradip K. Jha. RT Component Sets for High-Level Design Applications |
| 167 | -- | 182 | Ian G. Harris, Alex Orailoglu. Module Selection in Microarchitectural Synthesis for Multiple Critical Constraint Satisfaction |
| 183 | -- | 193 | Jen-Pin Weng, Alice C. Parker. Taking Thermal Considerations Into Account During High-Level Synthesis |
| 195 | -- | 209 | Allen C.-H. Wu. Datapath Optimization Using Layout Information: An Empirical Study |
| 211 | -- | 221 | Fur-Shing Tsai, Yu-Chin Hsu. Layout Modeling and Design Space Exploration in Pss1 System |