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Profile Name

sandrobartolini

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Publications: 4
Edited: 0

Aliases

Bartolini, Sandro
Bartolini, S.
Sandro Bartolini
Bartolini
S. Bartolini

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Sandro Bartolini's Profile

Publications

Unidentified Publications

Publications with a 'Sandro Bartolini' as author, editor, or advisor:

Software-Based Fault-Detection Technique for Object Tracking in Autonomous VehiclesAlessio Medaglini, Sandro Bartolini, Gianluca Mandò, Eduardo Quiñones, Sara Royuela. meco 2023: 1-7 [doi]
Scalable Path-Setup Scheme for All-Optical Dynamic Circuit Switched NoCs in Cache Coherent CMPsPaolo Grani, Sandro Bartolini. jetc, 14(1), 2018. [doi]
Memory performance: dealing with applications, systems and architectureSandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete. sigarch, 34(1):1-2, 2006. [doi]
An Object Level Transformation Technique to Improve the Performance of Embedded ApplicationsSandro Bartolini, Cosimo Antonio Prete. Source Code Analysis and Manipulation, IEEE International Workshop on, 0, 2001. [doi]
Flexible task-DAG management in PHAST library: Data-parallel tasks and orchestration support for heterogeneous systemsBiagio Peccerillo, Sandro Bartolini. concurrency, 34(2), 2022. [doi]
Simultaneous Optical Path-Setup for Reconfigurable Photonic Networks in Tiled CMPsPaolo Grani, Sandro Bartolini. hpcc 2014: 482-485 [doi]
PHAST Library - Enabling Single-Source and High Performance Code for GPUs and Multi-coresBiagio Peccerillo, Sandro Bartolini. ieeehpcs 2017: 715-718 [doi]
Feedback-Driven Restructuring of Multi-threaded Applications for NUCA Cache Performance in CMPsSandro Bartolini, Pierfrancesco Foglia, Marco Solinas, Cosimo Antonio Prete. sbac-pad 2010: 87-94 [doi]
Integration of RISC-V Page Table Walk in gem5 SE ModeMirco Mannino, Yinting Huang, Biagio Peccerillo, Alessio Medaglini, Sandro Bartolini. rapido 2024: 22-28 [doi]
Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysisLuca Ramini, Paolo Grani, Sandro Bartolini, Davide Bertozzi. date 2013: 1589-1594 [doi]
Eighth MEDEA WorkshopSandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete. thipeac, 3:91-92, 2011. [doi]
Inclusion of a Montgomery Multiplier Unit into an Embedded Processors Datapath to Speed-up Elliptic Curve CryptographySandro Bartolini, Cinzia Castagnini, Enrico Martinelli. IEEEias 2007: 95-100 [doi]
Design Options for Optical Ring Interconnect in Future Client DevicesPaolo Grani, Sandro Bartolini. jetc, 10(4):30, 2014. [doi]
A cache-aware program transformation technique suitable for embedded systemsSandro Bartolini, Cosimo Antonio Prete. INFSOF, 44(13):783-795, 2002.
Parallel bitsliced AES through PHAST: a single-source high-performance library for multi-cores and GPUsBiagio Peccerillo, Sandro Bartolini, Çetin Kaya Koç. jce, 9(2):159-171, 2019. [doi]
PHAST - A Portable High-Level Modern C++ Programming Library for GPUs and Multi-CoresBiagio Peccerillo, Sandro Bartolini. tpds, 30(1):174-189, 2019. [doi]
Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC 2016, Prague, Czech Republic, January 18, 2016Sören Sonntag, Sandro Bartolini, Giorgos Dimitrakopoulos, José M. García 0001, editors, ACM, 2016. [doi]
Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baselineLuca Ramini, Alberto Ghiribaldi, Paolo Grani, Sandro Bartolini, Hervé Tatenguem Fankem, Davide Bertozzi. date 2014: 1-6 [doi]
Proceedings of the 2004 workshop on MEmory performance - DEaling with Applications , systems and architecture, MEDEA '04, Antibes Juan-les-Pins, France, September 29 - October 3, 2004Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete, editors, ACM, 2004. [doi]
A proposal for input-sensitivity analysis of profile-driven optimizations on embedded applicationsSandro Bartolini, Cosimo Antonio Prete. sigarch, 32(3):70-77, 2004. [doi]
Adaptive Dosing Control System Through ARIMA Model for Peristaltic PumpsDavide Privitera, Stefano Bellissima, Sandro Bartolini. access, 11:99558-99572, 2023. [doi]
Embedded processors and systems: Architectural issues and solutions for emerging applicationsSandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete. jec, 2(1):1-3, 2006. [doi]
Solving Graph Partitioning Problems Arising in Tagless Cache ManagementSandro Bartolini, Iacopo Casini, Paolo Detti. iscopt 2014: 50-61 [doi]
Analysis and Optimization of Direct Convolution Execution on Multi-Core ProcessorsMirco Mannino, Biagio Peccerillo, Andrea Mondelli, Sandro Bartolini. access, 11:57514-57528, 2023. [doi]
Applying Intel's oneAPI to a machine learning case studyPablo Antonio Martínez, Biagio Peccerillo, Sandro Bartolini, José M. García 0001, Gregorio Bernabé. concurrency, 34(13), 2022. [doi]
Proceedings of the 9th workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '08, Toronto, Canada, October 26, 2008Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, Roberto Giorgi, editors, ACM, 2008. [doi]
MEmory performance: DEaling with applications, systems and architectureSandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete. sigarch, 35(4):4-5, 2007. [doi]
Proceedings of the 10th workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '09, Raleigh, North Carolina, USA, September 13, 2009Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete, editors, ACM, 2009. [doi]
Exploring the relationship between architectures and management policies in the design of NUCA-based chip multicore systemsSandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete. fgcs, 78:481-501, 2018. [doi]
Optimizing instruction cache performance of embedded systemsSandro Bartolini, Cosimo Antonio Prete. tecs, 4(4):934-965, 2005. [doi]
Task-DAG Support in Single-Source PHAST Library: Enabling Flexible Assignment of Tasks to CPUs and GPUs in Heterogeneous ArchitecturesBiagio Peccerillo, Sandro Bartolini. ppopp 2019: 91-100 [doi]
A General Framework for Accelerator Management Based on ISA ExtensionElham Cheshmikhani, Biagio Peccerillo, Andrea Mondelli, Sandro Bartolini. access, 10:120702-120713, 2022. [doi]
A survey on hardware accelerators: Taxonomy, trends, challenges, and perspectivesBiagio Peccerillo, Mirco Mannino, Andrea Mondelli, Sandro Bartolini. jsa, 129:102561, 2022. [doi]
Instruction Set Extensions for Cryptographic ApplicationsSandro Bartolini, Roberto Giorgi, Enrico Martinelli. In Çetin Kaya Koç, editor, Cryptographic Engineering. pages 191-233, Springer, 2009. [doi]
Performance portability in a real world application: PHAST applied to CaffePablo Antonio Martínez, Biagio Peccerillo, Sandro Bartolini, José M. García 0001, Gregorio Bernabé. ijhpca, 36(3):419-439, 2022. [doi]
Ensemble Methods for Peristaltic Pump Accuracy EnhancementDavide Privitera, Alessandro Mecocci, Sandro Bartolini. access, 13:125157-125179, 2025. [doi]
An Object Level Transformation Technique to Improve the Performance of Embedded ApplicationsSandro Bartolini, Cosimo Antonio Prete. SCAM 2001: 26-34 [doi]
Proceedings of the 2007 workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '07, Brasov, Romania, September 16, 2007Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, Roberto Giorgi, editors, ACM, 2007. [doi]
Instruction Cache Energy Saving Through Compiler Way-PlacementTimothy M. Jones, Sandro Bartolini, Bruno De Bus, John Cavazos, Michael F. P. O Boyle. date 2008: 1196-1201 [doi]
Exploiting silicon photonics for energy-efficient heterogeneous parallel architecturesSandro Bartolini, José M. García. concurrency, 26(15):2489-2491, 2014. [doi]
A Simple On-Chip Optical Interconnection for Improving Performance of Coherency Traffic in CMPsSandro Bartolini, Paolo Grani. dsd 2012: 312-318 [doi]
Parallel Programming in Cyber-Physical SystemsSandro Bartolini, Biagio Peccerillo. In Çetin Kaya Koç, editor, Cyber-Physical Systems Security. pages 111-134, Springer, 2018. [doi]
Co-tuning of a hybrid electronic-optical network for reducing energy consumption in embedded CMPsSandro Bartolini, Paolo Grani. isca 2013: 9-16 [doi]
Managing resources dynamically in hybrid photonic-electronic networks-on-chipAntonio García-Guirado, Ricardo Fernández Pascual, José M. García 0001, Sandro Bartolini. concurrency, 26(15):2530-2550, 2014. [doi]
Olympic: A Hierarchical All-Optical Photonic Network for Low-Power Chip MultiprocessorsSandro Bartolini, Luca Lusnig, Enrico Martinelli. dsd 2013: 56-59 [doi]
Augmented Virtuality for Coastal Management: A Holistic Use of In Situ and Remote Sensing for Large Scale Definition of Coastal DynamicsSandro Bartolini, Alessandro Mecocci, Alessandro Pozzebon, Claudia Zoppetti, Duccio Bertoni, Giovanni Sarti, Andrea Caiti, Riccardo Costanzi, Filippo Catani, Andrea Ciampalini, Sandro Moretti. ijgi, 7(3):92, 2018. [doi]
Link-time optimization for power efficiency in a tagless instruction cacheTimothy M. Jones, Sandro Bartolini, Jonas Maebe, Dominique Chanet. CGO 2011: 32-41 [doi]
Towards compelling cases for the viability of silicon-nanophotonic technology in future manycore systemsLuca Ramini, Hervé Tatenguem Fankem, Alberto Ghiribaldi, Paolo Grani, Marta Ortín-Obón, Anja Boos, Sandro Bartolini. nocs 2014: 170-171 [doi]
High-Performance Multi-Object Tracking for Autonomous Driving in Urban Scenarios With Heterogeneous Embedded BoardsAlessio Medaglini, Biagio Peccerillo, Sandro Bartolini. access, 13:8649-8663, 2025. [doi]
DeVAS: Decoupled Virtual Address SpacesMirco Mannino, Biagio Peccerillo, Andrea Mondelli, Sandro Bartolini. sbac-pad 2024: 182-193 [doi]
IXIAM: ISA EXtension for Integrated Accelerator ManagementBiagio Peccerillo, Elham Cheshmikhani, Mirco Mannino, Andrea Mondelli, Sandro Bartolini. access, 11:33768-33791, 2023. [doi]
Energy and Performance Improvements for Convolutional Accelerators Using Lightweight Address Translation SupportMirco Mannino, Biagio Peccerillo, Andrea Mondelli, Sandro Bartolini. cf 2023: 84-90 [doi]
Guests editor s introductionSandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete. sigarch, 33(3):1-2, 2005. [doi]
Boosting multi-socket cache-coherency with low-latency silicon photonic interconnectsPaolo Grani, Robert Hendry, Sandro Bartolini, Keren Bergman. iccnc 2015: 830-836 [doi]

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