The following publications are possibly variants of this publication:
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- Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAMChun-Seok Jeong, Changsik Yoo, Jae-Jin Lee, Joongsik Kih. esscirc 2004: 379-382 [doi]
- 17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVsWon-Joo Yun, Indal Song, Hanki Jeoung, Hundai Choi, Seok Ho Lee, Jun-Bae Kim, Chi-Wook Kim, Jung Hwan Choi, Seong-Jin Jang, Joo-Sun Choi. isscc 2015: 1-3 [doi]
- A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMsYoung-Jin Jeon, Joong-Ho Lee, Hyun-Chul Lee, Kyo Won Jin, Kyeong-Sik Min, Jin-Yong Chung, Hong June Park. jssc, 39(11):2087-2092, 2004. [doi]
- A 500MHz DLL with second order duty cycle corrector for low jitterByung-Guk Kim, Kwang-Il Oh, Lee-Sup Kim, Dae Woo Lee. cicc 2005: 325-328 [doi]
- A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMsJi-Hoon Lim, Jun-Hyun Bae, Jaemin Jang, Hae Kang Jung, Hyunbae Lee, Yongju Kim, Byungsub Kim, Jae-Yoon Sim, Hong June Park. tcas, 63-II(2):141-145, 2016. [doi]