The following publications are possibly variants of this publication:
- A Single Event Upset Resilient Latch Design with Single Node Upset ImmunityXixi Dai, Haibin Wang, Jiamin Chu, Zhi Liu, Li Cai, Kang Yan. et, 35(6):909-916, 2019. [doi]
- A single event upset tolerant latch with parallel nodesChangyong Liu, Nianlong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng 0001, Xiangdong Hu. ieiceee, 16(11):20190208, 2019. [doi]
- A single event upset tolerant latch designHaibin Wang, Xixi Dai, Yangsheng Wang, Issam Nofal, Li Cai, Zicai Shen, Wanxiu Sun, Jinshun Bi, Bo Li 0051, Gang Guo, Li Chen, Sang H. Baeg. mr, 88:909-913, 2018. [doi]
- Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power ApplicationsAibin Yan, Yuanjie Hu, Jie Song, Xiaoqing Wen. date 2019: 1679-1684 [doi]
- A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient CellsZhiyuan Song, Aibin Yan, Jie Cui 0004, Zhili Chen, Xuejun Li, Xiaoqing Wen, Chaoping Lai, Zhengfeng Huang, Huaguo Liang. itc-asia 2019: 139-144 [doi]
- A High-Performance and Low-Cost Single-Event Multiple-Node-Upsets Resilient Latch DesignZhongyang Liu, Haineng Zhang, Jianwei Jiang, Yanjie Jia, Yuqiao Xie, Shichang Zou, Zhengxuan Zhang. tvlsi, 30(12):1867-1877, 2022. [doi]