Krishnan Ramakrishnan - researchr alias

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2010

Investigating the impact of NBTI on different power saving cache strategiesAndrew J. Ricketts, J. Singh, Krishnan Ramakrishnan, Narayanan Vijaykrishnan, D. K. Pradhan. date 2010: 592-597 [doi]

A novel si-tunnel FET based SRAM design for ultra low-power 0.3V V::::::DD:::::: applicationsJ. Singh, Krishnan Ramakrishnan, S. Mookerjea, S. Datta, Narayanan Vijaykrishnan, D. K. Pradhan. aspdac 2010: 181-186 [doi]

2009

A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power ApplicationsSungmin Bae, Krishnan Ramakrishnan, Narayanan Vijaykrishnan. isvlsi 2009: 193-198 [doi]

A framework for estimating NBTI degradation of microarchitectural componentsMichael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan. aspdac 2009: 455-460 [doi]

::::New-Age::::: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural ComponentsMichael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang 0002, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan. ijpp, 37(4):417-431, 2009. [doi]

Process-Variation-Aware Adaptive Cache Architecture and ManagementMadhu Mutyam, Feng Wang 0004, Krishnan Ramakrishnan, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin. TC, 58(7):865-877, 2009. [doi]

Modeling Soft Errors at the Device and Logic Levels for Combinational CircuitsRajaraman Ramanarayanan, Vijay Degalahal, Krishnan Ramakrishnan, Jung Sub Kim, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Kenan Unlu. tdsc, 6(3):202-216, 2009. [doi]

2008

2007

Variation Impact on SER of Combinational CircuitsKrishnan Ramakrishnan, R. Rajaraman, S. Suresh, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. isqed 2007: 911-916 [doi]

Impact of NBTI on FPGAsKrishnan Ramakrishnan, S. Suresh, Narayanan Vijaykrishnan, Mary Jane Irwin. vlsid 2007: 717-722 [doi]